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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/mtd/nand/raw/davinci_nand.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
34  *
....@@ -7,27 +8,13 @@
78  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
89  *   Troy Kisky <troy.kisky@boundarydevices.com>
910  *   Dirk Behme <Dirk.Behme@gmail.com>
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License as published by
13
- * the Free Software Foundation; either version 2 of the License, or
14
- * (at your option) any later version.
15
- *
16
- * This program is distributed in the hope that it will be useful,
17
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
18
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
- * GNU General Public License for more details.
20
- *
21
- * You should have received a copy of the GNU General Public License
22
- * along with this program; if not, write to the Free Software
23
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
2411  */
2512 
2613 #include <linux/kernel.h>
2714 #include <linux/module.h>
2815 #include <linux/platform_device.h>
2916 #include <linux/err.h>
30
-#include <linux/io.h>
17
+#include <linux/iopoll.h>
3118 #include <linux/mtd/rawnand.h>
3219 #include <linux/mtd/partitions.h>
3320 #include <linux/slab.h>
....@@ -51,6 +38,7 @@
5138  * outputs in a "wire-AND" configuration, with no per-chip signals.
5239  */
5340 struct davinci_nand_info {
41
+	struct nand_controller	controller;
5442 	struct nand_chip	chip;
5543 
5644 	struct platform_device	*pdev;
....@@ -94,47 +82,6 @@
9482 /*----------------------------------------------------------------------*/
9583 
9684 /*
97
- * Access to hardware control lines:  ALE, CLE, secondary chipselect.
98
- */
99
-
100
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
101
-				   unsigned int ctrl)
102
-{
103
-	struct davinci_nand_info	*info = to_davinci_nand(mtd);
104
-	void __iomem			*addr = info->current_cs;
105
-	struct nand_chip		*nand = mtd_to_nand(mtd);
106
-
107
-	/* Did the control lines change? */
108
-	if (ctrl & NAND_CTRL_CHANGE) {
109
-		if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
110
-			addr += info->mask_cle;
111
-		else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
112
-			addr += info->mask_ale;
113
-
114
-		nand->IO_ADDR_W = addr;
115
-	}
116
-
117
-	if (cmd != NAND_CMD_NONE)
118
-		iowrite8(cmd, nand->IO_ADDR_W);
119
-}
120
-
121
-static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
122
-{
123
-	struct davinci_nand_info	*info = to_davinci_nand(mtd);
124
-
125
-	info->current_cs = info->vaddr;
126
-
127
-	/* maybe kick in a second chipselect */
128
-	if (chip > 0)
129
-		info->current_cs += info->mask_chipsel;
130
-
131
-	info->chip.IO_ADDR_W = info->current_cs;
132
-	info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
133
-}
134
-
135
-/*----------------------------------------------------------------------*/
136
-
137
-/*
13885  * 1-bit hardware ECC ... context maintained for each core chipselect
13986  */
14087 
....@@ -146,16 +93,16 @@
14693 			+ 4 * info->core_chipsel);
14794 }
14895 
149
-static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
96
+static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode)
15097 {
15198 	struct davinci_nand_info *info;
15299 	uint32_t nandcfr;
153100 	unsigned long flags;
154101 
155
-	info = to_davinci_nand(mtd);
102
+	info = to_davinci_nand(nand_to_mtd(chip));
156103 
157104 	/* Reset ECC hardware */
158
-	nand_davinci_readecc_1bit(mtd);
105
+	nand_davinci_readecc_1bit(nand_to_mtd(chip));
159106 
160107 	spin_lock_irqsave(&davinci_nand_lock, flags);
161108 
....@@ -170,10 +117,10 @@
170117 /*
171118  * Read hardware ECC value and pack into three bytes
172119  */
173
-static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
174
-				      const u_char *dat, u_char *ecc_code)
120
+static int nand_davinci_calculate_1bit(struct nand_chip *chip,
121
+				       const u_char *dat, u_char *ecc_code)
175122 {
176
-	unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
123
+	unsigned int ecc_val = nand_davinci_readecc_1bit(nand_to_mtd(chip));
177124 	unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
178125 
179126 	/* invert so that erased block ecc is correct */
....@@ -185,10 +132,9 @@
185132 	return 0;
186133 }
187134 
188
-static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
135
+static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
189136 				     u_char *read_ecc, u_char *calc_ecc)
190137 {
191
-	struct nand_chip *chip = mtd_to_nand(mtd);
192138 	uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
193139 					  (read_ecc[2] << 16);
194140 	uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
....@@ -222,7 +168,7 @@
222168 /*
223169  * 4-bit hardware ECC ... context maintained over entire AEMIF
224170  *
225
- * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
171
+ * This is a syndrome engine, but we avoid NAND_ECC_PLACEMENT_INTERLEAVED
226172  * since that forces use of a problematic "infix OOB" layout.
227173  * Among other things, it trashes manufacturer bad block markers.
228174  * Also, and specific to this hardware, it ECC-protects the "prepad"
....@@ -231,9 +177,9 @@
231177  * OOB without recomputing ECC.
232178  */
233179 
234
-static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
180
+static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode)
235181 {
236
-	struct davinci_nand_info *info = to_davinci_nand(mtd);
182
+	struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
237183 	unsigned long flags;
238184 	u32 val;
239185 
....@@ -266,10 +212,10 @@
266212 }
267213 
268214 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
269
-static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
270
-		const u_char *dat, u_char *ecc_code)
215
+static int nand_davinci_calculate_4bit(struct nand_chip *chip,
216
+				       const u_char *dat, u_char *ecc_code)
271217 {
272
-	struct davinci_nand_info *info = to_davinci_nand(mtd);
218
+	struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
273219 	u32 raw_ecc[4], *p;
274220 	unsigned i;
275221 
....@@ -303,11 +249,11 @@
303249 /* Correct up to 4 bits in data we just read, using state left in the
304250  * hardware plus the ecc_code computed when it was first written.
305251  */
306
-static int nand_davinci_correct_4bit(struct mtd_info *mtd,
307
-		u_char *data, u_char *ecc_code, u_char *null)
252
+static int nand_davinci_correct_4bit(struct nand_chip *chip, u_char *data,
253
+				     u_char *ecc_code, u_char *null)
308254 {
309255 	int i;
310
-	struct davinci_nand_info *info = to_davinci_nand(mtd);
256
+	struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
311257 	unsigned short ecc10[8];
312258 	unsigned short *ecc16;
313259 	u32 syndrome[4];
....@@ -425,51 +371,71 @@
425371 	return corrected;
426372 }
427373 
428
-/*----------------------------------------------------------------------*/
429
-
430
-/*
431
- * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
432
- * how these chips are normally wired.  This translates to both 8 and 16
433
- * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
374
+/**
375
+ * nand_davinci_read_page_hwecc_oob_first - Hardware ECC page read with ECC
376
+ *                                          data read from OOB area
377
+ * @chip: nand chip info structure
378
+ * @buf: buffer to store read data
379
+ * @oob_required: caller requires OOB data read to chip->oob_poi
380
+ * @page: page number to read
434381  *
435
- * For now we assume that configuration, or any other one which ignores
436
- * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
437
- * and have that transparently morphed into multiple NAND operations.
382
+ * Hardware ECC for large page chips, which requires the ECC data to be
383
+ * extracted from the OOB before the actual data is read.
438384  */
439
-static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
385
+static int nand_davinci_read_page_hwecc_oob_first(struct nand_chip *chip,
386
+						  uint8_t *buf,
387
+						  int oob_required, int page)
440388 {
441
-	struct nand_chip *chip = mtd_to_nand(mtd);
389
+	struct mtd_info *mtd = nand_to_mtd(chip);
390
+	int i, eccsize = chip->ecc.size, ret;
391
+	int eccbytes = chip->ecc.bytes;
392
+	int eccsteps = chip->ecc.steps;
393
+	uint8_t *p = buf;
394
+	uint8_t *ecc_code = chip->ecc.code_buf;
395
+	unsigned int max_bitflips = 0;
442396 
443
-	if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
444
-		ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
445
-	else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
446
-		ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
447
-	else
448
-		ioread8_rep(chip->IO_ADDR_R, buf, len);
449
-}
397
+	/* Read the OOB area first */
398
+	ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
399
+	if (ret)
400
+		return ret;
450401 
451
-static void nand_davinci_write_buf(struct mtd_info *mtd,
452
-		const uint8_t *buf, int len)
453
-{
454
-	struct nand_chip *chip = mtd_to_nand(mtd);
402
+	/* Move read cursor to start of page */
403
+	ret = nand_change_read_column_op(chip, 0, NULL, 0, false);
404
+	if (ret)
405
+		return ret;
455406 
456
-	if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
457
-		iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
458
-	else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
459
-		iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
460
-	else
461
-		iowrite8_rep(chip->IO_ADDR_R, buf, len);
462
-}
407
+	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
408
+					 chip->ecc.total);
409
+	if (ret)
410
+		return ret;
463411 
464
-/*
465
- * Check hardware register for wait status. Returns 1 if device is ready,
466
- * 0 if it is still busy.
467
- */
468
-static int nand_davinci_dev_ready(struct mtd_info *mtd)
469
-{
470
-	struct davinci_nand_info *info = to_davinci_nand(mtd);
412
+	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
413
+		int stat;
471414 
472
-	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
415
+		chip->ecc.hwctl(chip, NAND_ECC_READ);
416
+
417
+		ret = nand_read_data_op(chip, p, eccsize, false, false);
418
+		if (ret)
419
+			return ret;
420
+
421
+		stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
422
+		if (stat == -EBADMSG &&
423
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
424
+			/* check for empty pages with bitflips */
425
+			stat = nand_check_erased_ecc_chunk(p, eccsize,
426
+							   &ecc_code[i],
427
+							   eccbytes, NULL, 0,
428
+							   chip->ecc.strength);
429
+		}
430
+
431
+		if (stat < 0) {
432
+			mtd->ecc_stats.failed++;
433
+		} else {
434
+			mtd->ecc_stats.corrected += stat;
435
+			max_bitflips = max_t(unsigned int, max_bitflips, stat);
436
+		}
437
+	}
438
+	return max_bitflips;
473439 }
474440 
475441 /*----------------------------------------------------------------------*/
....@@ -560,11 +526,11 @@
560526 		if (!of_property_read_string(pdev->dev.of_node,
561527 			"ti,davinci-ecc-mode", &mode)) {
562528 			if (!strncmp("none", mode, 4))
563
-				pdata->ecc_mode = NAND_ECC_NONE;
529
+				pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE;
564530 			if (!strncmp("soft", mode, 4))
565
-				pdata->ecc_mode = NAND_ECC_SOFT;
531
+				pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
566532 			if (!strncmp("hw", mode, 2))
567
-				pdata->ecc_mode = NAND_ECC_HW;
533
+				pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
568534 		}
569535 		if (!of_property_read_u32(pdev->dev.of_node,
570536 			"ti,davinci-ecc-bits", &prop))
....@@ -615,22 +581,33 @@
615581 	if (IS_ERR(pdata))
616582 		return PTR_ERR(pdata);
617583 
618
-	switch (info->chip.ecc.mode) {
619
-	case NAND_ECC_NONE:
584
+	/* Use board-specific ECC config */
585
+	info->chip.ecc.engine_type = pdata->engine_type;
586
+	info->chip.ecc.placement = pdata->ecc_placement;
587
+
588
+	switch (info->chip.ecc.engine_type) {
589
+	case NAND_ECC_ENGINE_TYPE_NONE:
620590 		pdata->ecc_bits = 0;
621591 		break;
622
-	case NAND_ECC_SOFT:
592
+	case NAND_ECC_ENGINE_TYPE_SOFT:
623593 		pdata->ecc_bits = 0;
624594 		/*
625
-		 * This driver expects Hamming based ECC when ecc_mode is set
626
-		 * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
627
-		 * avoid adding an extra ->ecc_algo field to
628
-		 * davinci_nand_pdata.
595
+		 * This driver expects Hamming based ECC when engine_type is set
596
+		 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to
597
+		 * NAND_ECC_ALGO_HAMMING to avoid adding an extra ->ecc_algo
598
+		 * field to davinci_nand_pdata.
629599 		 */
630
-		info->chip.ecc.algo = NAND_ECC_HAMMING;
600
+		info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
631601 		break;
632
-	case NAND_ECC_HW:
602
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
633603 		if (pdata->ecc_bits == 4) {
604
+			int chunks = mtd->writesize / 512;
605
+
606
+			if (!chunks || mtd->oobsize < 16) {
607
+				dev_dbg(&info->pdev->dev, "too small\n");
608
+				return -EINVAL;
609
+			}
610
+
634611 			/*
635612 			 * No sanity checks:  CPUs must support this,
636613 			 * and the chips may not use NAND_BUSWIDTH_16.
....@@ -652,14 +629,35 @@
652629 			info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
653630 			info->chip.ecc.bytes = 10;
654631 			info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
655
-			info->chip.ecc.algo = NAND_ECC_BCH;
632
+			info->chip.ecc.algo = NAND_ECC_ALGO_BCH;
633
+
634
+			/*
635
+			 * Update ECC layout if needed ... for 1-bit HW ECC, the
636
+			 * default is OK, but it allocates 6 bytes when only 3
637
+			 * are needed (for each 512 bytes). For 4-bit HW ECC,
638
+			 * the default is not usable: 10 bytes needed, not 6.
639
+			 *
640
+			 * For small page chips, preserve the manufacturer's
641
+			 * badblock marking data ... and make sure a flash BBT
642
+			 * table marker fits in the free bytes.
643
+			 */
644
+			if (chunks == 1) {
645
+				mtd_set_ooblayout(mtd,
646
+						  &hwecc4_small_ooblayout_ops);
647
+			} else if (chunks == 4 || chunks == 8) {
648
+				mtd_set_ooblayout(mtd,
649
+						  nand_get_large_page_ooblayout());
650
+				info->chip.ecc.read_page = nand_davinci_read_page_hwecc_oob_first;
651
+			} else {
652
+				return -EIO;
653
+			}
656654 		} else {
657655 			/* 1bit ecc hamming */
658656 			info->chip.ecc.calculate = nand_davinci_calculate_1bit;
659657 			info->chip.ecc.correct = nand_davinci_correct_1bit;
660658 			info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
661659 			info->chip.ecc.bytes = 3;
662
-			info->chip.ecc.algo = NAND_ECC_HAMMING;
660
+			info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
663661 		}
664662 		info->chip.ecc.size = 512;
665663 		info->chip.ecc.strength = pdata->ecc_bits;
....@@ -668,39 +666,111 @@
668666 		return -EINVAL;
669667 	}
670668 
671
-	/*
672
-	 * Update ECC layout if needed ... for 1-bit HW ECC, the default
673
-	 * is OK, but it allocates 6 bytes when only 3 are needed (for
674
-	 * each 512 bytes).  For the 4-bit HW ECC, that default is not
675
-	 * usable:  10 bytes are needed, not 6.
676
-	 */
677
-	if (pdata->ecc_bits == 4) {
678
-		int chunks = mtd->writesize / 512;
669
+	return ret;
670
+}
679671 
680
-		if (!chunks || mtd->oobsize < 16) {
681
-			dev_dbg(&info->pdev->dev, "too small\n");
682
-			return -EINVAL;
683
-		}
672
+static void nand_davinci_data_in(struct davinci_nand_info *info, void *buf,
673
+				 unsigned int len, bool force_8bit)
674
+{
675
+	u32 alignment = ((uintptr_t)buf | len) & 3;
684676 
685
-		/* For small page chips, preserve the manufacturer's
686
-		 * badblock marking data ... and make sure a flash BBT
687
-		 * table marker fits in the free bytes.
688
-		 */
689
-		if (chunks == 1) {
690
-			mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
691
-		} else if (chunks == 4 || chunks == 8) {
692
-			mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
693
-			info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
694
-		} else {
695
-			return -EIO;
677
+	if (force_8bit || (alignment & 1))
678
+		ioread8_rep(info->current_cs, buf, len);
679
+	else if (alignment & 3)
680
+		ioread16_rep(info->current_cs, buf, len >> 1);
681
+	else
682
+		ioread32_rep(info->current_cs, buf, len >> 2);
683
+}
684
+
685
+static void nand_davinci_data_out(struct davinci_nand_info *info,
686
+				  const void *buf, unsigned int len,
687
+				  bool force_8bit)
688
+{
689
+	u32 alignment = ((uintptr_t)buf | len) & 3;
690
+
691
+	if (force_8bit || (alignment & 1))
692
+		iowrite8_rep(info->current_cs, buf, len);
693
+	else if (alignment & 3)
694
+		iowrite16_rep(info->current_cs, buf, len >> 1);
695
+	else
696
+		iowrite32_rep(info->current_cs, buf, len >> 2);
697
+}
698
+
699
+static int davinci_nand_exec_instr(struct davinci_nand_info *info,
700
+				   const struct nand_op_instr *instr)
701
+{
702
+	unsigned int i, timeout_us;
703
+	u32 status;
704
+	int ret;
705
+
706
+	switch (instr->type) {
707
+	case NAND_OP_CMD_INSTR:
708
+		iowrite8(instr->ctx.cmd.opcode,
709
+			 info->current_cs + info->mask_cle);
710
+		break;
711
+
712
+	case NAND_OP_ADDR_INSTR:
713
+		for (i = 0; i < instr->ctx.addr.naddrs; i++) {
714
+			iowrite8(instr->ctx.addr.addrs[i],
715
+				 info->current_cs + info->mask_ale);
696716 		}
717
+		break;
718
+
719
+	case NAND_OP_DATA_IN_INSTR:
720
+		nand_davinci_data_in(info, instr->ctx.data.buf.in,
721
+				     instr->ctx.data.len,
722
+				     instr->ctx.data.force_8bit);
723
+		break;
724
+
725
+	case NAND_OP_DATA_OUT_INSTR:
726
+		nand_davinci_data_out(info, instr->ctx.data.buf.out,
727
+				      instr->ctx.data.len,
728
+				      instr->ctx.data.force_8bit);
729
+		break;
730
+
731
+	case NAND_OP_WAITRDY_INSTR:
732
+		timeout_us = instr->ctx.waitrdy.timeout_ms * 1000;
733
+		ret = readl_relaxed_poll_timeout(info->base + NANDFSR_OFFSET,
734
+						 status, status & BIT(0), 100,
735
+						 timeout_us);
736
+		if (ret)
737
+			return ret;
738
+
739
+		break;
697740 	}
698741 
699
-	return ret;
742
+	if (instr->delay_ns)
743
+		ndelay(instr->delay_ns);
744
+
745
+	return 0;
746
+}
747
+
748
+static int davinci_nand_exec_op(struct nand_chip *chip,
749
+				const struct nand_operation *op,
750
+				bool check_only)
751
+{
752
+	struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
753
+	unsigned int i;
754
+
755
+	if (check_only)
756
+		return 0;
757
+
758
+	info->current_cs = info->vaddr + (op->cs * info->mask_chipsel);
759
+
760
+	for (i = 0; i < op->ninstrs; i++) {
761
+		int ret;
762
+
763
+		ret = davinci_nand_exec_instr(info, &op->instrs[i]);
764
+		if (ret)
765
+			return ret;
766
+	}
767
+
768
+	return 0;
700769 }
701770 
702771 static const struct nand_controller_ops davinci_nand_controller_ops = {
703772 	.attach_chip = davinci_nand_attach_chip,
773
+	.exec_op = davinci_nand_exec_op,
704774 };
705775 
706776 static int nand_davinci_probe(struct platform_device *pdev)
....@@ -764,11 +834,6 @@
764834 	mtd->dev.parent		= &pdev->dev;
765835 	nand_set_flash_node(&info->chip, pdev->dev.of_node);
766836 
767
-	info->chip.IO_ADDR_R	= vaddr;
768
-	info->chip.IO_ADDR_W	= vaddr;
769
-	info->chip.chip_delay	= 0;
770
-	info->chip.select_chip	= nand_davinci_select_chip;
771
-
772837 	/* options such as NAND_BBT_USE_FLASH */
773838 	info->chip.bbt_options	= pdata->bbt_options;
774839 	/* options such as 16-bit widths */
....@@ -785,17 +850,6 @@
785850 	info->mask_ale		= pdata->mask_ale ? : MASK_ALE;
786851 	info->mask_cle		= pdata->mask_cle ? : MASK_CLE;
787852 
788
-	/* Set address of hardware control function */
789
-	info->chip.cmd_ctrl	= nand_davinci_hwcontrol;
790
-	info->chip.dev_ready	= nand_davinci_dev_ready;
791
-
792
-	/* Speed up buffer I/O */
793
-	info->chip.read_buf     = nand_davinci_read_buf;
794
-	info->chip.write_buf    = nand_davinci_write_buf;
795
-
796
-	/* Use board-specific ECC config */
797
-	info->chip.ecc.mode	= pdata->ecc_mode;
798
-
799853 	spin_lock_irq(&davinci_nand_lock);
800854 
801855 	/* put CSxNAND into NAND mode */
....@@ -806,7 +860,9 @@
806860 	spin_unlock_irq(&davinci_nand_lock);
807861 
808862 	/* Scan to find existence of the device(s) */
809
-	info->chip.dummy_controller.ops = &davinci_nand_controller_ops;
863
+	nand_controller_init(&info->controller);
864
+	info->controller.ops = &davinci_nand_controller_ops;
865
+	info->chip.controller = &info->controller;
810866 	ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
811867 	if (ret < 0) {
812868 		dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
....@@ -835,13 +891,17 @@
835891 static int nand_davinci_remove(struct platform_device *pdev)
836892 {
837893 	struct davinci_nand_info *info = platform_get_drvdata(pdev);
894
+	struct nand_chip *chip = &info->chip;
895
+	int ret;
838896 
839897 	spin_lock_irq(&davinci_nand_lock);
840
-	if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
898
+	if (info->chip.ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)
841899 		ecc4_busy = false;
842900 	spin_unlock_irq(&davinci_nand_lock);
843901 
844
-	nand_release(&info->chip);
902
+	ret = mtd_device_unregister(nand_to_mtd(chip));
903
+	WARN_ON(ret);
904
+	nand_cleanup(chip);
845905 
846906 	return 0;
847907 }