~hc/RK356X_SDK_RELEASE.git

..	..	@@ -7,6 +7,7 @@
7	7	* Author: Jisheng Zhang <jszhang@kernel.org>
8	8	*/
9	9
	10	+#include <linux/acpi.h>
10	11	#include <linux/clk.h>
11	12	#include <linux/dma-mapping.h>
12	13	#include <linux/iopoll.h>
..	..	@@ -26,11 +27,15 @@
26	27	/* DWCMSHC specific Mode Select value */
27	28	#define DWCMSHC_CTRL_HS400 0x7
28	29
29		-#define DWCMSHC_VER_ID 0x500
30		-#define DWCMSHC_VER_TYPE 0x504
31		-#define DWCMSHC_HOST_CTRL3 0x508
32		-#define DWCMSHC_EMMC_CONTROL 0x52c
33		-#define DWCMSHC_EMMC_ATCTRL 0x540
	30	+/* DWC IP vendor area 1 pointer */
	31	+#define DWCMSHC_P_VENDOR_AREA1 0xe8
	32	+#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
	33	+/* Offset inside the vendor area 1 */
	34	+#define DWCMSHC_HOST_CTRL3 0x8
	35	+#define DWCMSHC_EMMC_CONTROL 0x2c
	36	+#define DWCMSHC_CARD_IS_EMMC BIT(0)
	37	+#define DWCMSHC_ENHANCED_STROBE BIT(8)
	38	+#define DWCMSHC_EMMC_ATCTRL 0x40
34	39
35	40	/* Rockchip specific Registers */
36	41	#define DWCMSHC_EMMC_DLL_CTRL 0x800
..	..	@@ -40,31 +45,30 @@
40	45	#define DECMSHC_EMMC_DLL_CMDOUT 0x810
41	46	#define DWCMSHC_EMMC_DLL_STATUS0 0x840
42	47	#define DWCMSHC_EMMC_DLL_STATUS1 0x844
43		-
44	48	#define DWCMSHC_EMMC_DLL_START BIT(0)
45	49	#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
46	50	#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
	51	+#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
47	52	#define DWCMSHC_EMMC_DLL_START_POINT 16
48	53	#define DWCMSHC_EMMC_DLL_INC 8
49	54	#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
50	55	#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
51		-
52	56	#define DLL_TAP_VALUE_SEL BIT(25)
53	57	#define DLL_TAP_VALUE_OFFSET 8
54		-
	58	+#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
	59	+#define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
55	60	#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
56		-#define DLL_TXCLK_NO_INVERTER BIT(29)
57		-
	61	+#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
58	62	#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
59	63	#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
60	64	#define DLL_STRBIN_DELAY_NUM_OFFSET 16
61		-
62		-#define DLL_RXCLK_NO_INVERTER BIT(29)
	65	+#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
	66	+#define DLL_RXCLK_NO_INVERTER 1
	67	+#define DLL_RXCLK_INVERTER 0
	68	+#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
	69	+#define DLL_RXCLK_TAPNUM_FROM_SW BIT(24)
63	70	#define DLL_RXCLK_ORI_GATE BIT(31)
64		-
65		-#define DWCMSHC_CARD_IS_EMMC BIT(0)
66		-#define DWCMSHC_ENHANCED_STROBE BIT(8)
67		-
	71	+#define DLL_RXCLK_MAX_TAP 32
68	72	#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
69	73	#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
70	74	#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
..	..	@@ -73,10 +77,15 @@
73	77	#define DLL_LOCK_WO_TMOUT(x) \
74	78	((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
75	79	(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
76		-#define ROCKCHIP_MAX_CLKS 3
	80	+#define RK35xx_MAX_CLKS 3
77	81
78	82	#define BOUNDARY_OK(addr, len) \
79	83	((addr \| (SZ_128M - 1)) == ((addr + len - 1) \| (SZ_128M - 1)))
	84	+
	85	+enum dwcmshc_rk_type {
	86	+ DWCMSHC_RK3568,
	87	+ DWCMSHC_RK3588,
	88	+};
80	89
81	90	struct dwcmshc_driver_data {
82	91	const struct sdhci_pltfm_data *pdata;
..	..	@@ -93,15 +102,22 @@
93	102	u8 hs400_strbin_tap;
94	103	};
95	104
96		-struct dwcmshc_priv {
97		- struct clk *bus_clk;
98		- u32 cclk_rate;
99		-
	105	+struct rk35xx_priv {
100	106	/* Rockchip specified optional clocks */
101		- struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS];
	107	+ struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
102	108	struct reset_control *reset;
	109	+ enum dwcmshc_rk_type devtype;
	110	+ u8 txclk_tapnum;
	111	+ u32 cclk_rate;
103	112	unsigned int actual_clk;
104	113	const struct dwcmshc_driver_data *drv_data;
	114	+ u32 acpi_en;
	115	+};
	116	+
	117	+struct dwcmshc_priv {
	118	+ struct clk *bus_clk;
	119	+ int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
	120	+ void priv; / pointer to SoC private stuff */
105	121	};
106	122
107	123	/*
..	..	@@ -125,6 +141,16 @@
125	141	addr += tmplen;
126	142	len -= tmplen;
127	143	sdhci_adma_write_desc(host, desc, addr, len, cmd);
	144	+}
	145	+
	146	+static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
	147	+{
	148	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	149	+
	150	+ if (pltfm_host->clk)
	151	+ return sdhci_pltfm_clk_get_max_clock(host);
	152	+ else
	153	+ return pltfm_host->clock;
128	154	}
129	155
130	156	static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
..	..	@@ -153,7 +179,9 @@
153	179	static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
154	180	unsigned int timing)
155	181	{
156		- u16 ctrl_2, ctrl;
	182	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	183	+ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	184	+ u16 ctrl, ctrl_2;
157	185
158	186	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
159	187	/* Select Bus Speed Mode for host */
..	..	@@ -173,9 +201,9 @@
173	201	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50;
174	202	else if (timing == MMC_TIMING_MMC_HS400) {
175	203	/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
176		- ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL);
	204	+ ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
177	205	ctrl \|= DWCMSHC_CARD_IS_EMMC;
178		- sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL);
	206	+ sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
179	207
180	208	ctrl_2 \|= DWCMSHC_CTRL_HS400;
181	209	}
..	..	@@ -188,22 +216,27 @@
188	216	{
189	217	u32 vendor;
190	218	struct sdhci_host *host = mmc_priv(mmc);
	219	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	220	+ struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	221	+ int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
191	222
192		- vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
	223	+ vendor = sdhci_readl(host, reg);
193	224	if (ios->enhanced_strobe)
194	225	vendor \|= DWCMSHC_ENHANCED_STROBE;
195	226	else
196	227	vendor &= ~DWCMSHC_ENHANCED_STROBE;
197	228
198		- sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
	229	+ sdhci_writel(host, vendor, reg);
199	230	}
200	231
201		-static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
	232	+static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
202	233	{
203	234	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
204		- struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	235	+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
	236	+ struct rk35xx_priv *priv = dwc_priv->priv;
205	237	const struct dwcmshc_driver_data *drv_data = priv->drv_data;
206		- u32 txclk_tapnum, extra, dll_lock_value;
	238	+ u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
	239	+ u32 extra, reg, dll_lock_value;
207	240	int err;
208	241
209	242	host->mmc->actual_clock = 0;
..	..	@@ -218,16 +251,28 @@
218	251	if (clock <= 400000)
219	252	clock = 375000;
220	253
221		- err = clk_set_rate(pltfm_host->clk, clock);
222		- if (err)
223		- dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
	254	+ if (priv->acpi_en) {
	255	+ union acpi_object params[1];
	256	+ struct acpi_object_list param_objects;
	257	+
	258	+ params[0].type = ACPI_TYPE_INTEGER;
	259	+ params[0].integer.value = clock;
	260	+ param_objects.count = 1;
	261	+ param_objects.pointer = params;
	262	+ acpi_evaluate_object(ACPI_HANDLE(mmc_dev(host->mmc)), "SCLK", &param_objects, NULL);
	263	+ } else {
	264	+ err = clk_set_rate(pltfm_host->clk, clock);
	265	+ if (err)
	266	+ dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
	267	+ }
224	268
225	269	sdhci_set_clock(host, clock);
226	270
227	271	/* Disable cmd conflict check */
228		- extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
	272	+ reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
	273	+ extra = sdhci_readl(host, reg);
229	274	extra &= ~BIT(0);
230		- sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
	275	+ sdhci_writel(host, extra, reg);
231	276
232	277	/* Disable output clock while config DLL */
233	278	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
..	..	@@ -262,6 +307,7 @@
262	307
263	308	/* Init DLL settings, clean start bit before resetting */
264	309	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
	310	+ /* Init DLL settings */
265	311	extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT \|
266	312	0x2 << DWCMSHC_EMMC_DLL_INC \|
267	313	DWCMSHC_EMMC_DLL_START;
..	..	@@ -279,33 +325,31 @@
279	325	extra = 0x1 << 16 \| /* tune clock stop en */
280	326	0x3 << 17 \| /* pre-change delay */
281	327	0x3 << 19; /* post-change delay */
282		- sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
	328	+ sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
283	329
284	330	extra = DWCMSHC_EMMC_DLL_DLYENA \| DLL_RXCLK_ORI_GATE;
285	331	if (drv_data->flags & RK_RXCLK_NO_INVERTER)
286		- extra \|= DLL_RXCLK_NO_INVERTER;
	332	+ extra \|= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
287	333	if (drv_data->flags & RK_TAP_VALUE_SEL)
288	334	extra \|= DLL_TAP_VALUE_SEL \| dll_lock_value << DLL_TAP_VALUE_OFFSET;
289	335	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
290	336
291	337	txclk_tapnum = drv_data->hs200_tx_tap;
292		- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
	338	+ if ((drv_data->flags & RK_DLL_CMD_OUT) &&
	339	+ host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
293	340	txclk_tapnum = drv_data->hs400_tx_tap;
294		-
295		- if (drv_data->flags & RK_DLL_CMD_OUT) {
296		- extra = DLL_CMDOUT_SRC_CLK_NEG \|
297		- DLL_CMDOUT_BOTH_CLK_EDGE \|
298		- DWCMSHC_EMMC_DLL_DLYENA \|
299		- drv_data->hs400_cmd_tap \|
300		- DLL_CMDOUT_TAPNUM_FROM_SW;
301		- if (drv_data->flags & RK_TAP_VALUE_SEL)
302		- extra \|= DLL_TAP_VALUE_SEL \| dll_lock_value << DLL_TAP_VALUE_OFFSET;
303		- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
304		- }
	341	+ extra = DLL_CMDOUT_SRC_CLK_NEG \|
	342	+ DLL_CMDOUT_BOTH_CLK_EDGE \|
	343	+ DWCMSHC_EMMC_DLL_DLYENA \|
	344	+ drv_data->hs400_cmd_tap \|
	345	+ DLL_CMDOUT_TAPNUM_FROM_SW;
	346	+ if (drv_data->flags & RK_TAP_VALUE_SEL)
	347	+ extra \|= DLL_TAP_VALUE_SEL \| dll_lock_value << DLL_TAP_VALUE_OFFSET;
	348	+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
305	349	}
306	350	extra = DWCMSHC_EMMC_DLL_DLYENA \|
307	351	DLL_TXCLK_TAPNUM_FROM_SW \|
308		- DLL_RXCLK_NO_INVERTER \|
	352	+ DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL \|
309	353	txclk_tapnum;
310	354	if (drv_data->flags & RK_TAP_VALUE_SEL)
311	355	extra \|= DLL_TAP_VALUE_SEL \| dll_lock_value << DLL_TAP_VALUE_OFFSET;
..	..	@@ -323,19 +367,16 @@
323	367	sdhci_enable_clk(host, 0);
324	368	}
325	369
326		-static void rockchip_sdhci_reset(struct sdhci_host *host, u8 mask)
	370	+static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
327	371	{
328		- struct sdhci_pltfm_host *pltfm_host;
329		- struct dwcmshc_priv *priv;
	372	+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	373	+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
	374	+ struct rk35xx_priv *priv = dwc_priv->priv;
330	375
331		- if (mask & SDHCI_RESET_ALL) {
332		- pltfm_host = sdhci_priv(host);
333		- priv = sdhci_pltfm_priv(pltfm_host);
334		- if (!IS_ERR_OR_NULL(priv->reset)) {
335		- reset_control_assert(priv->reset);
336		- udelay(1);
337		- reset_control_deassert(priv->reset);
338		- }
	376	+ if (mask & SDHCI_RESET_ALL && priv->reset) {
	377	+ reset_control_assert(priv->reset);
	378	+ udelay(1);
	379	+ reset_control_deassert(priv->reset);
339	380	}
340	381
341	382	sdhci_reset(host, mask);
..	..	@@ -353,17 +394,17 @@
353	394	.set_clock = sdhci_set_clock,
354	395	.set_bus_width = sdhci_set_bus_width,
355	396	.set_uhs_signaling = dwcmshc_set_uhs_signaling,
356		- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
	397	+ .get_max_clock = dwcmshc_get_max_clock,
357	398	.reset = sdhci_reset,
358	399	.adma_write_desc = dwcmshc_adma_write_desc,
359	400	};
360	401
361		-static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
362		- .set_clock = dwcmshc_rk_set_clock,
	402	+static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
	403	+ .set_clock = dwcmshc_rk3568_set_clock,
363	404	.set_bus_width = sdhci_set_bus_width,
364	405	.set_uhs_signaling = dwcmshc_set_uhs_signaling,
365	406	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
366		- .reset = rockchip_sdhci_reset,
	407	+ .reset = rk35xx_sdhci_reset,
367	408	.adma_write_desc = dwcmshc_adma_write_desc,
368	409	.request_done = sdhci_dwcmshc_request_done,
369	410	};
..	..	@@ -374,12 +415,76 @@
374	415	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
375	416	};
376	417
377		-static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = {
378		- .ops = &sdhci_dwcmshc_rk_ops,
	418	+#ifdef CONFIG_ACPI
	419	+static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
	420	+ .ops = &sdhci_dwcmshc_ops,
	421	+ .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	422	+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	423	+ SDHCI_QUIRK2_ACMD23_BROKEN,
	424	+};
	425	+#endif
	426	+
	427	+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
	428	+ .ops = &sdhci_dwcmshc_rk35xx_ops,
379	429	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
380	430	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
381	431	SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
382	432	};
	433	+
	434	+static int dwcmshc_rk35xx_init(struct sdhci_host host, struct dwcmshc_priv dwc_priv)
	435	+{
	436	+ int err;
	437	+ struct rk35xx_priv *priv = dwc_priv->priv;
	438	+
	439	+ priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
	440	+ if (IS_ERR(priv->reset)) {
	441	+ err = PTR_ERR(priv->reset);
	442	+ dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
	443	+ return err;
	444	+ }
	445	+
	446	+ priv->rockchip_clks[0].id = "axi";
	447	+ priv->rockchip_clks[1].id = "block";
	448	+ priv->rockchip_clks[2].id = "timer";
	449	+ err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
	450	+ priv->rockchip_clks);
	451	+ if (err) {
	452	+ dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
	453	+ return err;
	454	+ }
	455	+
	456	+ err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
	457	+ if (err) {
	458	+ dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
	459	+ return err;
	460	+ }
	461	+
	462	+ if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
	463	+ &priv->txclk_tapnum))
	464	+ priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
	465	+
	466	+ /* Disable cmd conflict check */
	467	+ sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
	468	+ /* Reset previous settings */
	469	+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
	470	+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
	471	+
	472	+ return 0;
	473	+}
	474	+
	475	+static void dwcmshc_rk35xx_postinit(struct sdhci_host host, struct dwcmshc_priv dwc_priv)
	476	+{
	477	+ /*
	478	+ * Don't support highspeed bus mode with low clk speed as we
	479	+ * cannot use DLL for this condition.
	480	+ */
	481	+ if (host->mmc->f_max <= 52000000) {
	482	+ dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
	483	+ host->mmc->f_max);
	484	+ host->mmc->caps2 &= ~(MMC_CAP2_HS200 \| MMC_CAP2_HS400);
	485	+ host->mmc->caps &= ~(MMC_CAP_3_3V_DDR \| MMC_CAP_1_8V_DDR);
	486	+ }
	487	+}
383	488
384	489	static const struct dwcmshc_driver_data dwcmshc_drvdata = {
385	490	.pdata = &sdhci_dwcmshc_pdata,
..	..	@@ -387,7 +492,7 @@
387	492	};
388	493
389	494	static const struct dwcmshc_driver_data rk3568_drvdata = {
390		- .pdata = &sdhci_dwcmshc_rk_pdata,
	495	+ .pdata = &sdhci_dwcmshc_rk35xx_pdata,
391	496	.flags = RK_PLATFROM \| RK_RXCLK_NO_INVERTER,
392	497	.hs200_tx_tap = 16,
393	498	.hs400_tx_tap = 8,
..	..	@@ -397,7 +502,7 @@
397	502	};
398	503
399	504	static const struct dwcmshc_driver_data rk3588_drvdata = {
400		- .pdata = &sdhci_dwcmshc_rk_pdata,
	505	+ .pdata = &sdhci_dwcmshc_rk35xx_pdata,
401	506	.flags = RK_PLATFROM \| RK_DLL_CMD_OUT,
402	507	.hs200_tx_tap = 16,
403	508	.hs400_tx_tap = 9,
..	..	@@ -407,7 +512,7 @@
407	512	};
408	513
409	514	static const struct dwcmshc_driver_data rk3528_drvdata = {
410		- .pdata = &sdhci_dwcmshc_rk_pdata,
	515	+ .pdata = &sdhci_dwcmshc_rk35xx_pdata,
411	516	.flags = RK_PLATFROM \| RK_DLL_CMD_OUT \| RK_TAP_VALUE_SEL,
412	517	.hs200_tx_tap = 12,
413	518	.hs400_tx_tap = 6,
..	..	@@ -416,51 +521,23 @@
416	521	.ddr50_strbin_delay_num = 10,
417	522	};
418	523
419		-static int rockchip_pltf_init(struct sdhci_host host, struct dwcmshc_priv priv)
420		-{
421		- int err;
422		-
423		- priv->rockchip_clks[0].id = "axi";
424		- priv->rockchip_clks[1].id = "block";
425		- priv->rockchip_clks[2].id = "timer";
426		- err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS,
427		- priv->rockchip_clks);
428		- if (err) {
429		- dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
430		- return err;
431		- }
432		-
433		- err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
434		- if (err) {
435		- dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
436		- return err;
437		- }
438		-
439		- /* Disable cmd conflict check */
440		- sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
441		- /* Reset previous settings */
442		- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
443		- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
444		-
445		- /*
446		- * Don't support highspeed bus mode with low clk speed as we
447		- * cannot use DLL for this condition.
448		- */
449		- if (host->mmc->f_max <= 52000000) {
450		- host->mmc->caps2 &= ~(MMC_CAP2_HS200 \| MMC_CAP2_HS400);
451		- host->mmc->caps &= ~(MMC_CAP_3_3V_DDR \| MMC_CAP_1_8V_DDR);
452		- }
453		-
454		- return 0;
455		-}
	524	+static const struct dwcmshc_driver_data rk3562_drvdata = {
	525	+ .pdata = &sdhci_dwcmshc_rk35xx_pdata,
	526	+ .flags = RK_PLATFROM \| RK_DLL_CMD_OUT \| RK_TAP_VALUE_SEL,
	527	+ .hs200_tx_tap = 12,
	528	+ .hs400_tx_tap = 6,
	529	+ .hs400_cmd_tap = 6,
	530	+ .hs400_strbin_tap = 3,
	531	+ .ddr50_strbin_delay_num = 10,
	532	+};
456	533
457	534	static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
458	535	{
459		- .compatible = "snps,dwcmshc-sdhci",
460		- .data = &dwcmshc_drvdata,
	536	+ .compatible = "rockchip,rk3588-dwcmshc",
	537	+ .data = &rk3588_drvdata,
461	538	},
462	539	{
463		- .compatible = "rockchip,dwcmshc-sdhci",
	540	+ .compatible = "rockchip,rk3568-dwcmshc",
464	541	.data = &rk3568_drvdata,
465	542	},
466	543	{
..	..	@@ -468,17 +545,35 @@
468	545	.data = &rk3528_drvdata,
469	546	},
470	547	{
471		- .compatible = "rockchip,rk3588-dwcmshc",
472		- .data = &rk3588_drvdata,
	548	+ .compatible = "rockchip,rk3562-dwcmshc",
	549	+ .data = &rk3562_drvdata,
	550	+ },
	551	+ {
	552	+ .compatible = "snps,dwcmshc-sdhci",
	553	+ .data = &dwcmshc_drvdata,
473	554	},
474	555	{},
475	556	};
	557	+MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
	558	+
	559	+#ifdef CONFIG_ACPI
	560	+static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
	561	+ {
	562	+ .id = "MLNXBF30",
	563	+ .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
	564	+ },
	565	+ {}
	566	+};
	567	+#endif
476	568
477	569	static int dwcmshc_probe(struct platform_device *pdev)
478	570	{
	571	+ struct device *dev = &pdev->dev;
479	572	struct sdhci_pltfm_host *pltfm_host;
480	573	struct sdhci_host *host;
481	574	struct dwcmshc_priv *priv;
	575	+ struct rk35xx_priv *rk_priv = NULL;
	576	+ const struct sdhci_pltfm_data *pltfm_data;
482	577	const struct dwcmshc_driver_data *drv_data;
483	578	struct mmc_hsq *hsq;
484	579	int err;
..	..	@@ -489,8 +584,9 @@
489	584	dev_err(&pdev->dev, "Error: No device match data found\n");
490	585	return -ENODEV;
491	586	}
	587	+ pltfm_data = drv_data->pdata;
492	588
493		- host = sdhci_pltfm_init(pdev, drv_data->pdata,
	589	+ host = sdhci_pltfm_init(pdev, pltfm_data,
494	590	sizeof(struct dwcmshc_priv));
495	591	if (IS_ERR(host))
496	592	return PTR_ERR(host);
..	..	@@ -498,34 +594,38 @@
498	594	/*
499	595	* extra adma table cnt for cross 128M boundary handling.
500	596	*/
501		- extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
	597	+ extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
502	598	if (extra > SDHCI_MAX_SEGS)
503	599	extra = SDHCI_MAX_SEGS;
504	600	host->adma_table_cnt += extra;
505	601
506	602	pltfm_host = sdhci_priv(host);
507	603	priv = sdhci_pltfm_priv(pltfm_host);
508		- priv->drv_data = drv_data;
509		- priv->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
510		- pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
511		- if (IS_ERR(pltfm_host->clk)) {
512		- err = PTR_ERR(pltfm_host->clk);
513		- dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
514		- goto free_pltfm;
515		- }
516		- err = clk_prepare_enable(pltfm_host->clk);
517		- if (err)
518		- goto free_pltfm;
519	604
520		- priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
521		- if (!IS_ERR(priv->bus_clk))
522		- clk_prepare_enable(priv->bus_clk);
	605	+ if (dev->of_node) {
	606	+ pltfm_host->clk = devm_clk_get(dev, "core");
	607	+ if (IS_ERR(pltfm_host->clk)) {
	608	+ err = PTR_ERR(pltfm_host->clk);
	609	+ dev_err(dev, "failed to get core clk: %d\n", err);
	610	+ goto free_pltfm;
	611	+ }
	612	+ err = clk_prepare_enable(pltfm_host->clk);
	613	+ if (err)
	614	+ goto free_pltfm;
	615	+
	616	+ priv->bus_clk = devm_clk_get(dev, "bus");
	617	+ if (!IS_ERR(priv->bus_clk))
	618	+ clk_prepare_enable(priv->bus_clk);
	619	+ }
523	620
524	621	err = mmc_of_parse(host->mmc);
525	622	if (err)
526	623	goto err_clk;
527	624
528	625	sdhci_get_of_property(pdev);
	626	+
	627	+ priv->vendor_specific_area1 =
	628	+ sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
529	629
530	630	host->mmc_host_ops.request = dwcmshc_request;
531	631	host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
..	..	@@ -540,29 +640,60 @@
540	640	if (err)
541	641	goto err_clk;
542	642
543		- err = sdhci_add_host(host);
544		- if (err)
545		- goto err_clk;
546		-
547	643	if (drv_data->flags & RK_PLATFROM) {
548		- err = rockchip_pltf_init(host, priv);
	644	+ rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
	645	+ if (!rk_priv) {
	646	+ err = -ENOMEM;
	647	+ goto err_clk;
	648	+ }
	649	+
	650	+ rk_priv->drv_data = drv_data;
	651	+ rk_priv->acpi_en = has_acpi_companion(&pdev->dev);
	652	+
	653	+ if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
	654	+ rk_priv->devtype = DWCMSHC_RK3588;
	655	+ else
	656	+ rk_priv->devtype = DWCMSHC_RK3568;
	657	+
	658	+ priv->priv = rk_priv;
	659	+
	660	+ err = dwcmshc_rk35xx_init(host, priv);
549	661	if (err)
550	662	goto err_clk;
551	663	}
552	664
553		- pm_runtime_get_noresume(&pdev->dev);
554		- pm_runtime_set_active(&pdev->dev);
555		- pm_runtime_enable(&pdev->dev);
556		- pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
557		- pm_runtime_use_autosuspend(&pdev->dev);
558		- pm_runtime_put_autosuspend(&pdev->dev);
	665	+ host->mmc->caps \|= MMC_CAP_WAIT_WHILE_BUSY;
	666	+
	667	+ err = sdhci_setup_host(host);
	668	+ if (err)
	669	+ goto err_clk;
	670	+
	671	+ if (rk_priv)
	672	+ dwcmshc_rk35xx_postinit(host, priv);
	673	+
	674	+ err = __sdhci_add_host(host);
	675	+ if (err)
	676	+ goto err_setup_host;
	677	+
	678	+ if (rk_priv && !rk_priv->acpi_en) {
	679	+ pm_runtime_get_noresume(&pdev->dev);
	680	+ pm_runtime_set_active(&pdev->dev);
	681	+ pm_runtime_enable(&pdev->dev);
	682	+ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	683	+ pm_runtime_use_autosuspend(&pdev->dev);
	684	+ pm_runtime_put_autosuspend(&pdev->dev);
	685	+ }
559	686
560	687	return 0;
561	688
	689	+err_setup_host:
	690	+ sdhci_cleanup_host(host);
562	691	err_clk:
563	692	clk_disable_unprepare(pltfm_host->clk);
564	693	clk_disable_unprepare(priv->bus_clk);
565		- clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
	694	+ if (rk_priv)
	695	+ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
	696	+ rk_priv->rockchip_clks);
566	697	free_pltfm:
567	698	sdhci_pltfm_free(pdev);
568	699	return err;
..	..	@@ -573,13 +704,15 @@
573	704	struct sdhci_host *host = platform_get_drvdata(pdev);
574	705	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575	706	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	707	+ struct rk35xx_priv *rk_priv = priv->priv;
576	708
577	709	sdhci_remove_host(host, 0);
578	710
579	711	clk_disable_unprepare(pltfm_host->clk);
580	712	clk_disable_unprepare(priv->bus_clk);
581		- clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
582		-
	713	+ if (rk_priv)
	714	+ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
	715	+ rk_priv->rockchip_clks);
583	716	sdhci_pltfm_free(pdev);
584	717
585	718	return 0;
..	..	@@ -591,6 +724,7 @@
591	724	struct sdhci_host *host = dev_get_drvdata(dev);
592	725	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
593	726	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	727	+ struct rk35xx_priv *rk_priv = priv->priv;
594	728	int ret;
595	729
596	730	mmc_hsq_suspend(host->mmc);
..	..	@@ -603,7 +737,10 @@
603	737	if (!IS_ERR(priv->bus_clk))
604	738	clk_disable_unprepare(priv->bus_clk);
605	739
606		- clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
	740	+ if (rk_priv)
	741	+ clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
	742	+ rk_priv->rockchip_clks);
	743	+
607	744	return ret;
608	745	}
609	746
..	..	@@ -612,6 +749,7 @@
612	749	struct sdhci_host *host = dev_get_drvdata(dev);
613	750	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
614	751	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
	752	+ struct rk35xx_priv *rk_priv = priv->priv;
615	753	int ret;
616	754
617	755	ret = clk_prepare_enable(pltfm_host->clk);
..	..	@@ -624,9 +762,12 @@
624	762	return ret;
625	763	}
626	764
627		- ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
628		- if (ret)
629		- return ret;
	765	+ if (rk_priv) {
	766	+ ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
	767	+ rk_priv->rockchip_clks);
	768	+ if (ret)
	769	+ return ret;
	770	+ }
630	771
631	772	ret = sdhci_resume_host(host);
632	773	if (ret)
..	..	@@ -664,13 +805,13 @@
664	805	SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
665	806	SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL)
666	807	};
667		-MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
668	808
669	809	static struct platform_driver sdhci_dwcmshc_driver = {
670	810	.driver = {
671	811	.name = "sdhci-dwcmshc",
672	812	.probe_type = PROBE_PREFER_ASYNCHRONOUS,
673	813	.of_match_table = sdhci_dwcmshc_dt_ids,
	814	+ .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
674	815	.pm = &dwcmshc_pmops,
675	816	},
676	817	.probe = dwcmshc_probe,