forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/misc/cardreader/rtsx_pcr.c
....@@ -1,19 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /* Driver for Realtek PCI-Express card reader
23  *
34  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of the GNU General Public License as published by the
7
- * Free Software Foundation; either version 2, or (at your option) any
8
- * later version.
9
- *
10
- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along
16
- * with this program; if not, see <http://www.gnu.org/licenses/>.
175  *
186  * Author:
197  *   Wei WANG <wei_wang@realsil.com.cn>
....@@ -34,6 +22,8 @@
3422 #include <asm/unaligned.h>
3523 
3624 #include "rtsx_pcr.h"
25
+#include "rts5261.h"
26
+#include "rts5228.h"
3727 
3828 static bool msi_en = true;
3929 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
....@@ -45,9 +35,6 @@
4535 static struct mfd_cell rtsx_pcr_cells[] = {
4636 	[RTSX_SD_CARD] = {
4737 		.name = DRV_NAME_RTSX_PCI_SDMMC,
48
-	},
49
-	[RTSX_MS_CARD] = {
50
-		.name = DRV_NAME_RTSX_PCI_MS,
5138 	},
5239 };
5340 
....@@ -63,21 +50,17 @@
6350 	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
6451 	{ PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
6552 	{ PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53
+	{ PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
54
+	{ PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
6655 	{ 0, }
6756 };
6857 
6958 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
7059 
71
-static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
72
-{
73
-	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
74
-		0xFC, pcr->aspm_en);
75
-}
76
-
7760 static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
7861 {
79
-	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
80
-		0xFC, 0);
62
+	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
63
+					   PCI_EXP_LNKCTL_ASPMC, 0);
8164 }
8265 
8366 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
....@@ -98,32 +81,17 @@
9881 
9982 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
10083 {
101
-	if (pcr->ops->set_ltr_latency)
102
-		return pcr->ops->set_ltr_latency(pcr, latency);
103
-	else
104
-		return rtsx_comm_set_ltr_latency(pcr, latency);
84
+	return rtsx_comm_set_ltr_latency(pcr, latency);
10585 }
10686 
10787 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
10888 {
109
-	struct rtsx_cr_option *option = &pcr->option;
110
-
11189 	if (pcr->aspm_enabled == enable)
11290 		return;
11391 
114
-	if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
115
-		if (enable)
116
-			rtsx_pci_enable_aspm(pcr);
117
-		else
118
-			rtsx_pci_disable_aspm(pcr);
119
-	} else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
120
-		u8 mask = FORCE_ASPM_VAL_MASK;
121
-		u8 val = 0;
122
-
123
-		if (enable)
124
-			val = pcr->aspm_en;
125
-		rtsx_pci_write_register(pcr, ASPM_FORCE_CTL,  mask, val);
126
-	}
92
+	pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
93
+					   PCI_EXP_LNKCTL_ASPMC,
94
+					   enable ? pcr->aspm_en : 0);
12795 
12896 	pcr->aspm_enabled = enable;
12997 }
....@@ -167,10 +135,7 @@
167135 
168136 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
169137 {
170
-	if (pcr->ops->full_on)
171
-		pcr->ops->full_on(pcr);
172
-	else
173
-		rtsx_comm_pm_full_on(pcr);
138
+	rtsx_comm_pm_full_on(pcr);
174139 }
175140 
176141 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
....@@ -243,16 +208,10 @@
243208 	int err, i, finished = 0;
244209 	u8 tmp;
245210 
246
-	rtsx_pci_init_cmd(pcr);
247
-
248
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
249
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
250
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
251
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
252
-
253
-	err = rtsx_pci_send_cmd(pcr, 100);
254
-	if (err < 0)
255
-		return err;
211
+	rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
212
+	rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
213
+	rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
214
+	rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
256215 
257216 	for (i = 0; i < 100000; i++) {
258217 		err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
....@@ -284,16 +243,10 @@
284243 {
285244 	int err, i, finished = 0;
286245 	u16 data;
287
-	u8 *ptr, tmp;
246
+	u8 tmp, val1, val2;
288247 
289
-	rtsx_pci_init_cmd(pcr);
290
-
291
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
292
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
293
-
294
-	err = rtsx_pci_send_cmd(pcr, 100);
295
-	if (err < 0)
296
-		return err;
248
+	rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
249
+	rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
297250 
298251 	for (i = 0; i < 100000; i++) {
299252 		err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
....@@ -309,17 +262,9 @@
309262 	if (!finished)
310263 		return -ETIMEDOUT;
311264 
312
-	rtsx_pci_init_cmd(pcr);
313
-
314
-	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
315
-	rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
316
-
317
-	err = rtsx_pci_send_cmd(pcr, 100);
318
-	if (err < 0)
319
-		return err;
320
-
321
-	ptr = rtsx_pci_get_cmd_data(pcr);
322
-	data = ((u16)ptr[1] << 8) | ptr[0];
265
+	rtsx_pci_read_register(pcr, PHYDATA0, &val1);
266
+	rtsx_pci_read_register(pcr, PHYDATA1, &val2);
267
+	data = val1 | (val2 << 8);
323268 
324269 	if (val)
325270 		*val = data;
....@@ -453,8 +398,16 @@
453398 
454399 	if (end)
455400 		option |= RTSX_SG_END;
456
-	val = ((u64)addr << 32) | ((u64)len << 12) | option;
457401 
402
+	if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
403
+		if (len > 0xFFFF)
404
+			val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
405
+				| (((u64)len >> 16) << 6) | option;
406
+		else
407
+			val = ((u64)addr << 32) | ((u64)len << 16) | option;
408
+	} else {
409
+		val = ((u64)addr << 32) | ((u64)len << 12) | option;
410
+	}
458411 	put_unaligned_le64(val, ptr);
459412 	pcr->sgi++;
460413 }
....@@ -699,14 +652,16 @@
699652 	else
700653 		return -EINVAL;
701654 
702
-
703655 	return rtsx_pci_set_pull_ctl(pcr, tbl);
704656 }
705657 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
706658 
707659 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
708660 {
709
-	pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
661
+	struct rtsx_hw_param *hw_param = &pcr->hw_param;
662
+
663
+	pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
664
+		| hw_param->interrupt_en;
710665 
711666 	if (pcr->num_slots > 1)
712667 		pcr->bier |= MS_INT_EN;
....@@ -746,6 +701,13 @@
746701 		[RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
747702 		[RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
748703 	};
704
+
705
+	if (PCI_PID(pcr) == PID_5261)
706
+		return rts5261_pci_switch_clock(pcr, card_clock,
707
+				ssc_depth, initial_mode, double_clk, vpclk);
708
+	if (PCI_PID(pcr) == PID_5228)
709
+		return rts5228_pci_switch_clock(pcr, card_clock,
710
+				ssc_depth, initial_mode, double_clk, vpclk);
749711 
750712 	if (initial_mode) {
751713 		/* We use 250k(around) here, in initial stage */
....@@ -972,8 +934,19 @@
972934 
973935 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
974936 {
975
-	if (pcr->ops->process_ocp)
937
+	if (pcr->ops->process_ocp) {
976938 		pcr->ops->process_ocp(pcr);
939
+	} else {
940
+		if (!pcr->option.ocp_en)
941
+			return;
942
+		rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
943
+		if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
944
+			rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
945
+			rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
946
+			rtsx_pci_clear_ocpstat(pcr);
947
+			pcr->ocp_stat = 0;
948
+		}
949
+	}
977950 }
978951 
979952 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
....@@ -1042,7 +1015,7 @@
10421015 		}
10431016 	}
10441017 
1045
-	if (pcr->card_inserted || pcr->card_removed)
1018
+	if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
10461019 		schedule_delayed_work(&pcr->carddet_work,
10471020 				msecs_to_jiffies(200));
10481021 
....@@ -1099,10 +1072,7 @@
10991072 
11001073 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
11011074 {
1102
-	if (pcr->ops->power_saving)
1103
-		pcr->ops->power_saving(pcr);
1104
-	else
1105
-		rtsx_comm_pm_power_saving(pcr);
1075
+	rtsx_comm_pm_power_saving(pcr);
11061076 }
11071077 
11081078 static void rtsx_pci_idle_work(struct work_struct *work)
....@@ -1126,8 +1096,21 @@
11261096 	mutex_unlock(&pcr->pcr_mutex);
11271097 }
11281098 
1129
-#ifdef CONFIG_PM
1130
-static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
1099
+static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
1100
+{
1101
+	/* Set relink_time to 0 */
1102
+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1103
+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1104
+	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1105
+			RELINK_TIME_MASK, 0);
1106
+
1107
+	rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1108
+			D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
1109
+
1110
+	rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1111
+}
1112
+
1113
+static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
11311114 {
11321115 	if (pcr->ops->turn_off_led)
11331116 		pcr->ops->turn_off_led(pcr);
....@@ -1140,17 +1123,20 @@
11401123 
11411124 	if (pcr->ops->force_power_down)
11421125 		pcr->ops->force_power_down(pcr, pm_state);
1126
+	else
1127
+		rtsx_base_force_power_down(pcr, pm_state);
11431128 }
1144
-#endif
11451129 
11461130 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
11471131 {
11481132 	u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
11491133 
1150
-	if (pcr->ops->enable_ocp)
1134
+	if (pcr->ops->enable_ocp) {
11511135 		pcr->ops->enable_ocp(pcr);
1152
-	else
1136
+	} else {
1137
+		rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
11531138 		rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1139
+	}
11541140 
11551141 }
11561142 
....@@ -1158,10 +1144,13 @@
11581144 {
11591145 	u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
11601146 
1161
-	if (pcr->ops->disable_ocp)
1147
+	if (pcr->ops->disable_ocp) {
11621148 		pcr->ops->disable_ocp(pcr);
1163
-	else
1149
+	} else {
11641150 		rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1151
+		rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1152
+				OC_POWER_DOWN);
1153
+	}
11651154 }
11661155 
11671156 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
....@@ -1172,7 +1161,7 @@
11721161 		struct rtsx_cr_option *option = &(pcr->option);
11731162 
11741163 		if (option->ocp_en) {
1175
-			u8 val = option->sd_400mA_ocp_thd;
1164
+			u8 val = option->sd_800mA_ocp_thd;
11761165 
11771166 			rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
11781167 			rtsx_pci_write_register(pcr, REG_OCPPARA1,
....@@ -1182,10 +1171,6 @@
11821171 			rtsx_pci_write_register(pcr, REG_OCPGLITCH,
11831172 				SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
11841173 			rtsx_pci_enable_ocp(pcr);
1185
-		} else {
1186
-			/* OC power down */
1187
-			rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1188
-				OC_POWER_DOWN);
11891174 		}
11901175 	}
11911176 }
....@@ -1207,8 +1192,39 @@
12071192 		u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
12081193 
12091194 		rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1195
+		udelay(100);
12101196 		rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
12111197 	}
1198
+}
1199
+
1200
+void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1201
+{
1202
+	u16 val;
1203
+
1204
+	if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1205
+		rtsx_pci_read_phy_register(pcr, 0x01, &val);
1206
+		val |= 1<<9;
1207
+		rtsx_pci_write_phy_register(pcr, 0x01, val);
1208
+	}
1209
+	rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1210
+	rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1211
+	rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1212
+	rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1213
+
1214
+}
1215
+
1216
+void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1217
+{
1218
+	u16 val;
1219
+
1220
+	if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1221
+		rtsx_pci_read_phy_register(pcr, 0x01, &val);
1222
+		val &= ~(1<<9);
1223
+		rtsx_pci_write_phy_register(pcr, 0x01, val);
1224
+	}
1225
+	rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1226
+	rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1227
+
12121228 }
12131229 
12141230 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
....@@ -1216,7 +1232,6 @@
12161232 	rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
12171233 		MS_CLK_EN | SD40_CLK_EN, 0);
12181234 	rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1219
-
12201235 	rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
12211236 
12221237 	msleep(50);
....@@ -1241,15 +1256,27 @@
12411256 
12421257 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
12431258 {
1259
+	struct pci_dev *pdev = pcr->pci;
12441260 	int err;
12451261 
1246
-	pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
1262
+	if (PCI_PID(pcr) == PID_5228)
1263
+		rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1264
+				RTS5228_LDO1_SR_0_5);
1265
+
12471266 	rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
12481267 
12491268 	rtsx_pci_enable_bus_int(pcr);
12501269 
12511270 	/* Power on SSC */
1252
-	err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1271
+	if (PCI_PID(pcr) == PID_5261) {
1272
+		/* Gating real mcu clock */
1273
+		err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1274
+			RTS5261_MCU_CLOCK_GATING, 0);
1275
+		err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1276
+			SSC_POWER_DOWN, 0);
1277
+	} else {
1278
+		err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1279
+	}
12531280 	if (err < 0)
12541281 		return err;
12551282 
....@@ -1279,7 +1306,15 @@
12791306 	/* Enable SSC Clock */
12801307 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
12811308 			0xFF, SSC_8X_EN | SSC_SEL_4M);
1282
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1309
+	if (PCI_PID(pcr) == PID_5261)
1310
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1311
+			RTS5261_SSC_DEPTH_2M);
1312
+	else if (PCI_PID(pcr) == PID_5228)
1313
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1314
+			RTS5228_SSC_DEPTH_2M);
1315
+	else
1316
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1317
+
12831318 	/* Disable cd_pwr_save */
12841319 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
12851320 	/* Clear Link Ready Interrupt */
....@@ -1310,16 +1345,22 @@
13101345 	case PID_524A:
13111346 	case PID_525A:
13121347 	case PID_5260:
1348
+	case PID_5261:
1349
+	case PID_5228:
13131350 		rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
13141351 		break;
13151352 	default:
13161353 		break;
13171354 	}
13181355 
1356
+	/*init ocp*/
1357
+	rtsx_pci_init_ocp(pcr);
1358
+
13191359 	/* Enable clk_request_n to enable clock power management */
1320
-	rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1360
+	pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
1361
+				   PCI_EXP_LNKCTL_CLKREQ_EN);
13211362 	/* Enter L1 when host tx idle */
1322
-	rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1363
+	pci_write_config_byte(pdev, 0x70F, 0x5B);
13231364 
13241365 	if (pcr->ops->extra_init_hw) {
13251366 		err = pcr->ops->extra_init_hw(pcr);
....@@ -1386,8 +1427,17 @@
13861427 	case 0x5286:
13871428 		rtl8402_init_params(pcr);
13881429 		break;
1430
+
13891431 	case 0x5260:
13901432 		rts5260_init_params(pcr);
1433
+		break;
1434
+
1435
+	case 0x5261:
1436
+		rts5261_init_params(pcr);
1437
+		break;
1438
+
1439
+	case 0x5228:
1440
+		rts5228_init_params(pcr);
13911441 		break;
13921442 	}
13931443 
....@@ -1476,10 +1526,10 @@
14761526 		bar = 1;
14771527 	len = pci_resource_len(pcidev, bar);
14781528 	base = pci_resource_start(pcidev, bar);
1479
-	pcr->remap_addr = ioremap_nocache(base, len);
1529
+	pcr->remap_addr = ioremap(base, len);
14801530 	if (!pcr->remap_addr) {
14811531 		ret = -ENOMEM;
1482
-		goto free_handle;
1532
+		goto free_idr;
14831533 	}
14841534 
14851535 	pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
....@@ -1541,6 +1591,10 @@
15411591 			pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
15421592 unmap:
15431593 	iounmap(pcr->remap_addr);
1594
+free_idr:
1595
+	spin_lock(&rtsx_pci_lock);
1596
+	idr_remove(&rtsx_pci_idr, pcr->id);
1597
+	spin_unlock(&rtsx_pci_lock);
15441598 free_handle:
15451599 	kfree(handle);
15461600 free_pcr:
....@@ -1594,10 +1648,9 @@
15941648 		pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
15951649 }
15961650 
1597
-#ifdef CONFIG_PM
1598
-
1599
-static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1651
+static int __maybe_unused rtsx_pci_suspend(struct device *dev_d)
16001652 {
1653
+	struct pci_dev *pcidev = to_pci_dev(dev_d);
16011654 	struct pcr_handle *handle;
16021655 	struct rtsx_pcr *pcr;
16031656 
....@@ -1613,17 +1666,15 @@
16131666 
16141667 	rtsx_pci_power_off(pcr, HOST_ENTER_S3);
16151668 
1616
-	pci_save_state(pcidev);
1617
-	pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1618
-	pci_disable_device(pcidev);
1619
-	pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1669
+	device_wakeup_disable(dev_d);
16201670 
16211671 	mutex_unlock(&pcr->pcr_mutex);
16221672 	return 0;
16231673 }
16241674 
1625
-static int rtsx_pci_resume(struct pci_dev *pcidev)
1675
+static int __maybe_unused rtsx_pci_resume(struct device *dev_d)
16261676 {
1677
+	struct pci_dev *pcidev = to_pci_dev(dev_d);
16271678 	struct pcr_handle *handle;
16281679 	struct rtsx_pcr *pcr;
16291680 	int ret = 0;
....@@ -1634,13 +1685,6 @@
16341685 	pcr = handle->pcr;
16351686 
16361687 	mutex_lock(&pcr->pcr_mutex);
1637
-
1638
-	pci_set_power_state(pcidev, PCI_D0);
1639
-	pci_restore_state(pcidev);
1640
-	ret = pci_enable_device(pcidev);
1641
-	if (ret)
1642
-		goto out;
1643
-	pci_set_master(pcidev);
16441688 
16451689 	ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
16461690 	if (ret)
....@@ -1656,6 +1700,8 @@
16561700 	mutex_unlock(&pcr->pcr_mutex);
16571701 	return ret;
16581702 }
1703
+
1704
+#ifdef CONFIG_PM
16591705 
16601706 static void rtsx_pci_shutdown(struct pci_dev *pcidev)
16611707 {
....@@ -1676,19 +1722,18 @@
16761722 
16771723 #else /* CONFIG_PM */
16781724 
1679
-#define rtsx_pci_suspend NULL
1680
-#define rtsx_pci_resume NULL
16811725 #define rtsx_pci_shutdown NULL
16821726 
16831727 #endif /* CONFIG_PM */
1728
+
1729
+static SIMPLE_DEV_PM_OPS(rtsx_pci_pm_ops, rtsx_pci_suspend, rtsx_pci_resume);
16841730 
16851731 static struct pci_driver rtsx_pci_driver = {
16861732 	.name = DRV_NAME_RTSX_PCI,
16871733 	.id_table = rtsx_pci_ids,
16881734 	.probe = rtsx_pci_probe,
16891735 	.remove = rtsx_pci_remove,
1690
-	.suspend = rtsx_pci_suspend,
1691
-	.resume = rtsx_pci_resume,
1736
+	.driver.pm = &rtsx_pci_pm_ops,
16921737 	.shutdown = rtsx_pci_shutdown,
16931738 };
16941739 module_pci_driver(rtsx_pci_driver);