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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/media/platform/ti-vpe/cal_regs.h
....@@ -1,19 +1,38 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * TI CAL camera interface driver
34  *
45  * Copyright (c) 2015 Texas Instruments Inc.
56  *
67  * Benoit Parrot, <bparrot@ti.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms of the GNU General Public License version 2 as published by
10
- * the Free Software Foundation.
118  */
129 
1310 #ifndef __TI_CAL_REGS_H
1411 #define __TI_CAL_REGS_H
1512 
16
-#define CAL_NUM_CSI2_PORTS		2
13
+/*
14
+ * struct cal_dev.flags possibilities
15
+ *
16
+ * DRA72_CAL_PRE_ES2_LDO_DISABLE:
17
+ *   Errata i913: CSI2 LDO Needs to be disabled when module is powered on
18
+ *
19
+ *   Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
20
+ *   LDOs on the device are disabled if CSI-2 module is powered on
21
+ *   (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
22
+ *   | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
23
+ *   current draw on the module supply in active mode.
24
+ *
25
+ *   Errata does not apply when CSI-2 module is powered off
26
+ *   (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
27
+ *
28
+ * SW Workaround:
29
+ *	Set the following register bits to disable the LDO,
30
+ *	which is essentially CSI2 REG10 bit 6:
31
+ *
32
+ *		Core 0:  0x4845 B828 = 0x0000 0040
33
+ *		Core 1:  0x4845 B928 = 0x0000 0040
34
+ */
35
+#define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
1736 
1837 /* CAL register offsets */
1938 
....@@ -21,11 +40,11 @@
2140 #define CAL_HL_HWINFO			0x0004
2241 #define CAL_HL_SYSCONFIG		0x0010
2342 #define CAL_HL_IRQ_EOI			0x001c
24
-#define CAL_HL_IRQSTATUS_RAW(m)		(0x20U + ((m-1) * 0x10U))
25
-#define CAL_HL_IRQSTATUS(m)		(0x24U + ((m-1) * 0x10U))
26
-#define CAL_HL_IRQENABLE_SET(m)		(0x28U + ((m-1) * 0x10U))
27
-#define CAL_HL_IRQENABLE_CLR(m)		(0x2cU + ((m-1) * 0x10U))
28
-#define CAL_PIX_PROC(m)			(0xc0U + ((m-1) * 0x4U))
43
+#define CAL_HL_IRQSTATUS_RAW(m)		(0x20U + (m) * 0x10U)
44
+#define CAL_HL_IRQSTATUS(m)		(0x24U + (m) * 0x10U)
45
+#define CAL_HL_IRQENABLE_SET(m)		(0x28U + (m) * 0x10U)
46
+#define CAL_HL_IRQENABLE_CLR(m)		(0x2cU + (m) * 0x10U)
47
+#define CAL_PIX_PROC(m)			(0xc0U + (m) * 0x4U)
2948 #define CAL_CTRL			0x100
3049 #define CAL_CTRL1			0x104
3150 #define CAL_LINE_NUMBER_EVT		0x108
....@@ -41,51 +60,43 @@
4160 #define CAL_RD_DMA_INIT_ADDR		0x154
4261 #define CAL_RD_DMA_INIT_OFST		0x168
4362 #define CAL_RD_DMA_CTRL2		0x16c
44
-#define CAL_WR_DMA_CTRL(m)		(0x200U + ((m-1) * 0x10U))
45
-#define CAL_WR_DMA_ADDR(m)		(0x204U + ((m-1) * 0x10U))
46
-#define CAL_WR_DMA_OFST(m)		(0x208U + ((m-1) * 0x10U))
47
-#define CAL_WR_DMA_XSIZE(m)		(0x20cU + ((m-1) * 0x10U))
48
-#define CAL_CSI2_PPI_CTRL(m)		(0x300U + ((m-1) * 0x80U))
49
-#define CAL_CSI2_COMPLEXIO_CFG(m)	(0x304U + ((m-1) * 0x80U))
50
-#define CAL_CSI2_COMPLEXIO_IRQSTATUS(m)	(0x308U + ((m-1) * 0x80U))
51
-#define CAL_CSI2_SHORT_PACKET(m)	(0x30cU + ((m-1) * 0x80U))
52
-#define CAL_CSI2_COMPLEXIO_IRQENABLE(m)	(0x310U + ((m-1) * 0x80U))
53
-#define CAL_CSI2_TIMING(m)		(0x314U + ((m-1) * 0x80U))
54
-#define CAL_CSI2_VC_IRQENABLE(m)	(0x318U + ((m-1) * 0x80U))
55
-#define CAL_CSI2_VC_IRQSTATUS(m)	(0x328U + ((m-1) * 0x80U))
56
-#define CAL_CSI2_CTX0(m)		(0x330U + ((m-1) * 0x80U))
57
-#define CAL_CSI2_CTX1(m)		(0x334U + ((m-1) * 0x80U))
58
-#define CAL_CSI2_CTX2(m)		(0x338U + ((m-1) * 0x80U))
59
-#define CAL_CSI2_CTX3(m)		(0x33cU + ((m-1) * 0x80U))
60
-#define CAL_CSI2_CTX4(m)		(0x340U + ((m-1) * 0x80U))
61
-#define CAL_CSI2_CTX5(m)		(0x344U + ((m-1) * 0x80U))
62
-#define CAL_CSI2_CTX6(m)		(0x348U + ((m-1) * 0x80U))
63
-#define CAL_CSI2_CTX7(m)		(0x34cU + ((m-1) * 0x80U))
64
-#define CAL_CSI2_STATUS0(m)		(0x350U + ((m-1) * 0x80U))
65
-#define CAL_CSI2_STATUS1(m)		(0x354U + ((m-1) * 0x80U))
66
-#define CAL_CSI2_STATUS2(m)		(0x358U + ((m-1) * 0x80U))
67
-#define CAL_CSI2_STATUS3(m)		(0x35cU + ((m-1) * 0x80U))
68
-#define CAL_CSI2_STATUS4(m)		(0x360U + ((m-1) * 0x80U))
69
-#define CAL_CSI2_STATUS5(m)		(0x364U + ((m-1) * 0x80U))
70
-#define CAL_CSI2_STATUS6(m)		(0x368U + ((m-1) * 0x80U))
71
-#define CAL_CSI2_STATUS7(m)		(0x36cU + ((m-1) * 0x80U))
63
+#define CAL_WR_DMA_CTRL(m)		(0x200U + (m) * 0x10U)
64
+#define CAL_WR_DMA_ADDR(m)		(0x204U + (m) * 0x10U)
65
+#define CAL_WR_DMA_OFST(m)		(0x208U + (m) * 0x10U)
66
+#define CAL_WR_DMA_XSIZE(m)		(0x20cU + (m) * 0x10U)
67
+#define CAL_CSI2_PPI_CTRL(m)		(0x300U + (m) * 0x80U)
68
+#define CAL_CSI2_COMPLEXIO_CFG(m)	(0x304U + (m) * 0x80U)
69
+#define CAL_CSI2_COMPLEXIO_IRQSTATUS(m)	(0x308U + (m) * 0x80U)
70
+#define CAL_CSI2_SHORT_PACKET(m)	(0x30cU + (m) * 0x80U)
71
+#define CAL_CSI2_COMPLEXIO_IRQENABLE(m)	(0x310U + (m) * 0x80U)
72
+#define CAL_CSI2_TIMING(m)		(0x314U + (m) * 0x80U)
73
+#define CAL_CSI2_VC_IRQENABLE(m)	(0x318U + (m) * 0x80U)
74
+#define CAL_CSI2_VC_IRQSTATUS(m)	(0x328U + (m) * 0x80U)
75
+#define CAL_CSI2_CTX0(m)		(0x330U + (m) * 0x80U)
76
+#define CAL_CSI2_CTX1(m)		(0x334U + (m) * 0x80U)
77
+#define CAL_CSI2_CTX2(m)		(0x338U + (m) * 0x80U)
78
+#define CAL_CSI2_CTX3(m)		(0x33cU + (m) * 0x80U)
79
+#define CAL_CSI2_CTX4(m)		(0x340U + (m) * 0x80U)
80
+#define CAL_CSI2_CTX5(m)		(0x344U + (m) * 0x80U)
81
+#define CAL_CSI2_CTX6(m)		(0x348U + (m) * 0x80U)
82
+#define CAL_CSI2_CTX7(m)		(0x34cU + (m) * 0x80U)
83
+#define CAL_CSI2_STATUS0(m)		(0x350U + (m) * 0x80U)
84
+#define CAL_CSI2_STATUS1(m)		(0x354U + (m) * 0x80U)
85
+#define CAL_CSI2_STATUS2(m)		(0x358U + (m) * 0x80U)
86
+#define CAL_CSI2_STATUS3(m)		(0x35cU + (m) * 0x80U)
87
+#define CAL_CSI2_STATUS4(m)		(0x360U + (m) * 0x80U)
88
+#define CAL_CSI2_STATUS5(m)		(0x364U + (m) * 0x80U)
89
+#define CAL_CSI2_STATUS6(m)		(0x368U + (m) * 0x80U)
90
+#define CAL_CSI2_STATUS7(m)		(0x36cU + (m) * 0x80U)
7291 
7392 /* CAL CSI2 PHY register offsets */
7493 #define CAL_CSI2_PHY_REG0		0x000
7594 #define CAL_CSI2_PHY_REG1		0x004
7695 #define CAL_CSI2_PHY_REG2		0x008
96
+#define CAL_CSI2_PHY_REG10		0x028
7797 
7898 /* CAL Control Module Core Camerrx Control register offsets */
7999 #define CM_CTRL_CORE_CAMERRX_CONTROL	0x000
80
-
81
-/*********************************************************************
82
-* Generic value used in various field below
83
-*********************************************************************/
84
-
85
-#define CAL_GEN_DISABLE			0
86
-#define CAL_GEN_ENABLE			1
87
-#define CAL_GEN_FALSE			0
88
-#define CAL_GEN_TRUE			1
89100 
90101 /*********************************************************************
91102 * Field Definition Macros
....@@ -113,7 +124,7 @@
113124 #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT		2
114125 #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED		3
115126 
116
-#define CAL_HL_SYSCONFIG_SOFTRESET_MASK		BIT_MASK(0)
127
+#define CAL_HL_SYSCONFIG_SOFTRESET_MASK		BIT(0)
117128 #define CAL_HL_SYSCONFIG_SOFTRESET_DONE			0x0
118129 #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING		0x1
119130 #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION		0x0
....@@ -124,19 +135,18 @@
124135 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1		2
125136 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2		3
126137 
127
-#define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK		BIT_MASK(0)
138
+#define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK		BIT(0)
128139 #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0		0
129140 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0			0
130141 
131
-#define CAL_HL_IRQ_MASK(m)			BIT_MASK(m-1)
132
-#define CAL_HL_IRQ_NOACTION				0x0
133
-#define CAL_HL_IRQ_ENABLE				0x1
134
-#define CAL_HL_IRQ_CLEAR				0x1
135
-#define CAL_HL_IRQ_DISABLED				0x0
136
-#define CAL_HL_IRQ_ENABLED				0x1
137
-#define CAL_HL_IRQ_PENDING				0x1
142
+#define CAL_HL_IRQ_MASK(m)			BIT(m)
138143 
139
-#define CAL_PIX_PROC_EN_MASK			BIT_MASK(0)
144
+#define CAL_HL_IRQ_OCPO_ERR_MASK		BIT(6)
145
+
146
+#define CAL_HL_IRQ_CIO_MASK(i)			BIT(16 + (i) * 8)
147
+#define CAL_HL_IRQ_VC_MASK(i)			BIT(17 + (i) * 8)
148
+
149
+#define CAL_PIX_PROC_EN_MASK			BIT(0)
140150 #define CAL_PIX_PROC_EXTRACT_MASK		GENMASK(4, 1)
141151 #define CAL_PIX_PROC_EXTRACT_B6				0x0
142152 #define CAL_PIX_PROC_EXTRACT_B7				0x1
....@@ -182,7 +192,7 @@
182192 #define CAL_PIX_PROC_PACK_ARGB				0x6
183193 #define CAL_PIX_PROC_CPORT_MASK			GENMASK(23, 19)
184194 
185
-#define CAL_CTRL_POSTED_WRITES_MASK		BIT_MASK(0)
195
+#define CAL_CTRL_POSTED_WRITES_MASK		BIT(0)
186196 #define CAL_CTRL_POSTED_WRITES_NONPOSTED		0
187197 #define CAL_CTRL_POSTED_WRITES				1
188198 #define CAL_CTRL_TAGCNT_MASK			GENMASK(4, 1)
....@@ -193,10 +203,10 @@
193203 #define CAL_CTRL_BURSTSIZE_BURST128			0x3
194204 #define CAL_CTRL_LL_FORCE_STATE_MASK		GENMASK(12, 7)
195205 #define CAL_CTRL_MFLAGL_MASK			GENMASK(20, 13)
196
-#define CAL_CTRL_PWRSCPCLK_MASK			BIT_MASK(21)
206
+#define CAL_CTRL_PWRSCPCLK_MASK			BIT(21)
197207 #define CAL_CTRL_PWRSCPCLK_AUTO				0
198208 #define CAL_CTRL_PWRSCPCLK_FORCE			1
199
-#define CAL_CTRL_RD_DMA_STALL_MASK		BIT_MASK(22)
209
+#define CAL_CTRL_RD_DMA_STALL_MASK		BIT(22)
200210 #define CAL_CTRL_MFLAGH_MASK			GENMASK(31, 24)
201211 
202212 #define CAL_CTRL1_PPI_GROUPING_MASK		GENMASK(1, 0)
....@@ -221,18 +231,18 @@
221231 #define CAL_VPORT_CTRL1_PCLK_MASK		GENMASK(16, 0)
222232 #define CAL_VPORT_CTRL1_XBLK_MASK		GENMASK(24, 17)
223233 #define CAL_VPORT_CTRL1_YBLK_MASK		GENMASK(30, 25)
224
-#define CAL_VPORT_CTRL1_WIDTH_MASK		BIT_MASK(31)
234
+#define CAL_VPORT_CTRL1_WIDTH_MASK		BIT(31)
225235 #define CAL_VPORT_CTRL1_WIDTH_ONE			0
226236 #define CAL_VPORT_CTRL1_WIDTH_TWO			1
227237 
228238 #define CAL_VPORT_CTRL2_CPORT_MASK		GENMASK(4, 0)
229
-#define CAL_VPORT_CTRL2_FREERUNNING_MASK	BIT_MASK(15)
239
+#define CAL_VPORT_CTRL2_FREERUNNING_MASK	BIT(15)
230240 #define CAL_VPORT_CTRL2_FREERUNNING_GATED		0
231241 #define CAL_VPORT_CTRL2_FREERUNNING_FREE		1
232
-#define CAL_VPORT_CTRL2_FS_RESETS_MASK		BIT_MASK(16)
242
+#define CAL_VPORT_CTRL2_FS_RESETS_MASK		BIT(16)
233243 #define CAL_VPORT_CTRL2_FS_RESETS_NO			0
234244 #define CAL_VPORT_CTRL2_FS_RESETS_YES			1
235
-#define CAL_VPORT_CTRL2_FSM_RESET_MASK		BIT_MASK(17)
245
+#define CAL_VPORT_CTRL2_FSM_RESET_MASK		BIT(17)
236246 #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT		0
237247 #define CAL_VPORT_CTRL2_FSM_RESET			1
238248 #define CAL_VPORT_CTRL2_RDY_THR_MASK		GENMASK(31, 18)
....@@ -240,23 +250,23 @@
240250 #define CAL_BYS_CTRL1_PCLK_MASK			GENMASK(16, 0)
241251 #define CAL_BYS_CTRL1_XBLK_MASK			GENMASK(24, 17)
242252 #define CAL_BYS_CTRL1_YBLK_MASK			GENMASK(30, 25)
243
-#define CAL_BYS_CTRL1_BYSINEN_MASK		BIT_MASK(31)
253
+#define CAL_BYS_CTRL1_BYSINEN_MASK		BIT(31)
244254 
245255 #define CAL_BYS_CTRL2_CPORTIN_MASK		GENMASK(4, 0)
246256 #define CAL_BYS_CTRL2_CPORTOUT_MASK		GENMASK(9, 5)
247
-#define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK	BIT_MASK(10)
257
+#define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK	BIT(10)
248258 #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO			0
249259 #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES		1
250
-#define CAL_BYS_CTRL2_FREERUNNING_MASK		BIT_MASK(11)
260
+#define CAL_BYS_CTRL2_FREERUNNING_MASK		BIT(11)
251261 #define CAL_BYS_CTRL2_FREERUNNING_NO			0
252262 #define CAL_BYS_CTRL2_FREERUNNING_YES			1
253263 
254
-#define CAL_RD_DMA_CTRL_GO_MASK			BIT_MASK(0)
264
+#define CAL_RD_DMA_CTRL_GO_MASK			BIT(0)
255265 #define CAL_RD_DMA_CTRL_GO_DIS				0
256266 #define CAL_RD_DMA_CTRL_GO_EN				1
257267 #define CAL_RD_DMA_CTRL_GO_IDLE				0
258268 #define CAL_RD_DMA_CTRL_GO_BUSY				1
259
-#define CAL_RD_DMA_CTRL_INIT_MASK		BIT_MASK(1)
269
+#define CAL_RD_DMA_CTRL_INIT_MASK		BIT(1)
260270 #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK		GENMASK(10, 2)
261271 #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK	GENMASK(14, 11)
262272 #define CAL_RD_DMA_CTRL_PCLK_MASK		GENMASK(31, 15)
....@@ -280,13 +290,13 @@
280290 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN		3
281291 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR		4
282292 #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED		5
283
-#define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK	BIT_MASK(3)
293
+#define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK	BIT(3)
284294 #define CAL_RD_DMA_CTRL2_PATTERN_MASK		GENMASK(5, 4)
285295 #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR			0
286296 #define CAL_RD_DMA_CTRL2_PATTERN_YUV420			1
287297 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2		2
288298 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4		3
289
-#define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK	BIT_MASK(6)
299
+#define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK	BIT(6)
290300 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING	0
291301 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT	1
292302 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK		GENMASK(29, 16)
....@@ -303,7 +313,7 @@
303313 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2		2
304314 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4		3
305315 #define CAL_WR_DMA_CTRL_PATTERN_RESERVED		1
306
-#define CAL_WR_DMA_CTRL_ICM_PSTART_MASK		BIT_MASK(5)
316
+#define CAL_WR_DMA_CTRL_ICM_PSTART_MASK		BIT(5)
307317 #define CAL_WR_DMA_CTRL_DTAG_MASK		GENMASK(8, 6)
308318 #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR			0
309319 #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT			1
....@@ -314,7 +324,7 @@
314324 #define CAL_WR_DMA_CTRL_DTAG_D6				6
315325 #define CAL_WR_DMA_CTRL_DTAG_D7				7
316326 #define CAL_WR_DMA_CTRL_CPORT_MASK		GENMASK(13, 9)
317
-#define CAL_WR_DMA_CTRL_STALL_RD_MASK		BIT_MASK(14)
327
+#define CAL_WR_DMA_CTRL_STALL_RD_MASK		BIT(14)
318328 #define CAL_WR_DMA_CTRL_YSIZE_MASK		GENMASK(31, 18)
319329 
320330 #define CAL_WR_DMA_ADDR_MASK			GENMASK(31, 4)
....@@ -330,9 +340,9 @@
330340 #define CAL_WR_DMA_XSIZE_XSKIP_MASK		GENMASK(15, 3)
331341 #define CAL_WR_DMA_XSIZE_MASK			GENMASK(31, 19)
332342 
333
-#define CAL_CSI2_PPI_CTRL_IF_EN_MASK		BIT_MASK(0)
334
-#define CAL_CSI2_PPI_CTRL_ECC_EN_MASK		BIT_MASK(2)
335
-#define CAL_CSI2_PPI_CTRL_FRAME_MASK		BIT_MASK(3)
343
+#define CAL_CSI2_PPI_CTRL_IF_EN_MASK		BIT(0)
344
+#define CAL_CSI2_PPI_CTRL_ECC_EN_MASK		BIT(2)
345
+#define CAL_CSI2_PPI_CTRL_FRAME_MASK		BIT(3)
336346 #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE		0
337347 #define CAL_CSI2_PPI_CTRL_FRAME				1
338348 
....@@ -343,18 +353,18 @@
343353 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2			2
344354 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1			1
345355 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED		0
346
-#define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK		BIT_MASK(3)
356
+#define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK		BIT(3)
347357 #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS			0
348358 #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS			1
349359 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK	GENMASK(6, 4)
350
-#define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK		BIT_MASK(7)
360
+#define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK		BIT(7)
351361 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK	GENMASK(10, 8)
352
-#define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK		BIT_MASK(11)
362
+#define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK		BIT(11)
353363 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK	GENMASK(14, 12)
354
-#define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK		BIT_MASK(15)
364
+#define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK		BIT(15)
355365 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK	GENMASK(18, 16)
356
-#define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK		BIT_MASK(19)
357
-#define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK		BIT_MASK(24)
366
+#define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK		BIT(19)
367
+#define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK		BIT(24)
358368 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK		GENMASK(26, 25)
359369 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF		0
360370 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON		1
....@@ -363,83 +373,84 @@
363373 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF		0
364374 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON			1
365375 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP		2
366
-#define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK		BIT_MASK(29)
376
+#define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK		BIT(29)
367377 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED	1
368378 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING		0
369
-#define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK		BIT_MASK(30)
379
+#define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK		BIT(30)
370380 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL			0
371381 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL		1
372382 
373383 #define CAL_CSI2_SHORT_PACKET_MASK	GENMASK(23, 0)
374384 
375
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK		BIT_MASK(0)
376
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK		BIT_MASK(1)
377
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK		BIT_MASK(2)
378
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK		BIT_MASK(3)
379
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK		BIT_MASK(4)
380
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK	BIT_MASK(5)
381
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK	BIT_MASK(6)
382
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK	BIT_MASK(7)
383
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK	BIT_MASK(8)
384
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK	BIT_MASK(9)
385
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK		BIT_MASK(10)
386
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK		BIT_MASK(11)
387
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK		BIT_MASK(12)
388
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK		BIT_MASK(13)
389
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK		BIT_MASK(14)
390
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK		BIT_MASK(15)
391
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK		BIT_MASK(16)
392
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK		BIT_MASK(17)
393
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK		BIT_MASK(18)
394
-#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK		BIT_MASK(19)
395
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK		BIT_MASK(20)
396
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK		BIT_MASK(21)
397
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK		BIT_MASK(22)
398
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK		BIT_MASK(23)
399
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK		BIT_MASK(24)
400
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK	BIT_MASK(25)
401
-#define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK	BIT_MASK(26)
402
-#define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK		BIT_MASK(27)
403
-#define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK	BIT_MASK(28)
404
-#define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK	BIT_MASK(30)
385
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK		BIT(0)
386
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK		BIT(1)
387
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK		BIT(2)
388
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK		BIT(3)
389
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK		BIT(4)
390
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK	BIT(5)
391
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK	BIT(6)
392
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK	BIT(7)
393
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK	BIT(8)
394
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK	BIT(9)
395
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK		BIT(10)
396
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK		BIT(11)
397
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK		BIT(12)
398
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK		BIT(13)
399
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK		BIT(14)
400
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK		BIT(15)
401
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK		BIT(16)
402
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK		BIT(17)
403
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK		BIT(18)
404
+#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK		BIT(19)
405
+#define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK		GENMASK(19, 0)
406
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK		BIT(20)
407
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK		BIT(21)
408
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK		BIT(22)
409
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK		BIT(23)
410
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK		BIT(24)
411
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK	BIT(25)
412
+#define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK	BIT(26)
413
+#define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK		BIT(27)
414
+#define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK	BIT(28)
415
+#define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK	BIT(30)
405416 
406417 #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK	GENMASK(12, 0)
407
-#define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK		BIT_MASK(13)
408
-#define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK		BIT_MASK(14)
409
-#define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK		BIT_MASK(15)
418
+#define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK		BIT(13)
419
+#define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK		BIT(14)
420
+#define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK		BIT(15)
410421 
411
-#define CAL_CSI2_VC_IRQ_FS_IRQ_0_MASK			BIT_MASK(0)
412
-#define CAL_CSI2_VC_IRQ_FE_IRQ_0_MASK			BIT_MASK(1)
413
-#define CAL_CSI2_VC_IRQ_LS_IRQ_0_MASK			BIT_MASK(2)
414
-#define CAL_CSI2_VC_IRQ_LE_IRQ_0_MASK			BIT_MASK(3)
415
-#define CAL_CSI2_VC_IRQ_CS_IRQ_0_MASK			BIT_MASK(4)
416
-#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_0_MASK	BIT_MASK(5)
417
-#define CAL_CSI2_VC_IRQ_FS_IRQ_1_MASK			BIT_MASK(8)
418
-#define CAL_CSI2_VC_IRQ_FE_IRQ_1_MASK			BIT_MASK(9)
419
-#define CAL_CSI2_VC_IRQ_LS_IRQ_1_MASK			BIT_MASK(10)
420
-#define CAL_CSI2_VC_IRQ_LE_IRQ_1_MASK			BIT_MASK(11)
421
-#define CAL_CSI2_VC_IRQ_CS_IRQ_1_MASK			BIT_MASK(12)
422
-#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_1_MASK	BIT_MASK(13)
423
-#define CAL_CSI2_VC_IRQ_FS_IRQ_2_MASK			BIT_MASK(16)
424
-#define CAL_CSI2_VC_IRQ_FE_IRQ_2_MASK			BIT_MASK(17)
425
-#define CAL_CSI2_VC_IRQ_LS_IRQ_2_MASK			BIT_MASK(18)
426
-#define CAL_CSI2_VC_IRQ_LE_IRQ_2_MASK			BIT_MASK(19)
427
-#define CAL_CSI2_VC_IRQ_CS_IRQ_2_MASK			BIT_MASK(20)
428
-#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_2_MASK	BIT_MASK(21)
429
-#define CAL_CSI2_VC_IRQ_FS_IRQ_3_MASK			BIT_MASK(24)
430
-#define CAL_CSI2_VC_IRQ_FE_IRQ_3_MASK			BIT_MASK(25)
431
-#define CAL_CSI2_VC_IRQ_LS_IRQ_3_MASK			BIT_MASK(26)
432
-#define CAL_CSI2_VC_IRQ_LE_IRQ_3_MASK			BIT_MASK(27)
433
-#define CAL_CSI2_VC_IRQ_CS_IRQ_3_MASK			BIT_MASK(28)
434
-#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_3_MASK	BIT_MASK(29)
422
+#define CAL_CSI2_VC_IRQ_FS_IRQ_0_MASK			BIT(0)
423
+#define CAL_CSI2_VC_IRQ_FE_IRQ_0_MASK			BIT(1)
424
+#define CAL_CSI2_VC_IRQ_LS_IRQ_0_MASK			BIT(2)
425
+#define CAL_CSI2_VC_IRQ_LE_IRQ_0_MASK			BIT(3)
426
+#define CAL_CSI2_VC_IRQ_CS_IRQ_0_MASK			BIT(4)
427
+#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_0_MASK	BIT(5)
428
+#define CAL_CSI2_VC_IRQ_FS_IRQ_1_MASK			BIT(8)
429
+#define CAL_CSI2_VC_IRQ_FE_IRQ_1_MASK			BIT(9)
430
+#define CAL_CSI2_VC_IRQ_LS_IRQ_1_MASK			BIT(10)
431
+#define CAL_CSI2_VC_IRQ_LE_IRQ_1_MASK			BIT(11)
432
+#define CAL_CSI2_VC_IRQ_CS_IRQ_1_MASK			BIT(12)
433
+#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_1_MASK	BIT(13)
434
+#define CAL_CSI2_VC_IRQ_FS_IRQ_2_MASK			BIT(16)
435
+#define CAL_CSI2_VC_IRQ_FE_IRQ_2_MASK			BIT(17)
436
+#define CAL_CSI2_VC_IRQ_LS_IRQ_2_MASK			BIT(18)
437
+#define CAL_CSI2_VC_IRQ_LE_IRQ_2_MASK			BIT(19)
438
+#define CAL_CSI2_VC_IRQ_CS_IRQ_2_MASK			BIT(20)
439
+#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_2_MASK	BIT(21)
440
+#define CAL_CSI2_VC_IRQ_FS_IRQ_3_MASK			BIT(24)
441
+#define CAL_CSI2_VC_IRQ_FE_IRQ_3_MASK			BIT(25)
442
+#define CAL_CSI2_VC_IRQ_LS_IRQ_3_MASK			BIT(26)
443
+#define CAL_CSI2_VC_IRQ_LE_IRQ_3_MASK			BIT(27)
444
+#define CAL_CSI2_VC_IRQ_CS_IRQ_3_MASK			BIT(28)
445
+#define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_3_MASK	BIT(29)
435446 
436447 #define CAL_CSI2_CTX_DT_MASK		GENMASK(5, 0)
437448 #define CAL_CSI2_CTX_VC_MASK		GENMASK(7, 6)
438449 #define CAL_CSI2_CTX_CPORT_MASK		GENMASK(12, 8)
439
-#define CAL_CSI2_CTX_ATT_MASK		BIT_MASK(13)
450
+#define CAL_CSI2_CTX_ATT_MASK		BIT(13)
440451 #define CAL_CSI2_CTX_ATT_PIX			0
441452 #define CAL_CSI2_CTX_ATT			1
442
-#define CAL_CSI2_CTX_PACK_MODE_MASK	BIT_MASK(14)
453
+#define CAL_CSI2_CTX_PACK_MODE_MASK	BIT(14)
443454 #define CAL_CSI2_CTX_PACK_MODE_LINE		0
444455 #define CAL_CSI2_CTX_PACK_MODE_FRAME		1
445456 #define CAL_CSI2_CTX_LINES_MASK		GENMASK(29, 16)
....@@ -448,7 +459,7 @@
448459 
449460 #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK	GENMASK(7, 0)
450461 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK		GENMASK(15, 8)
451
-#define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK	BIT_MASK(24)
462
+#define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK	BIT(24)
452463 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE		1
453464 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE		0
454465 
....@@ -456,10 +467,12 @@
456467 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK		GENMASK(9, 8)
457468 #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK		GENMASK(17, 10)
458469 #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK			GENMASK(24, 18)
459
-#define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK	BIT_MASK(25)
470
+#define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK	BIT(25)
460471 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR		1
461472 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS		0
462473 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK		GENMASK(29, 28)
474
+
475
+#define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK		BIT(6)
463476 
464477 #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK		GENMASK(23, 0)
465478 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK		GENMASK(25, 24)
....@@ -467,13 +480,13 @@
467480 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK		GENMASK(29, 28)
468481 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK		GENMASK(31, 30)
469482 
470
-#define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK			BIT_MASK(0)
483
+#define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK			BIT(0)
471484 #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK			GENMASK(2, 1)
472485 #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK			GENMASK(4, 3)
473
-#define CM_CAMERRX_CTRL_CSI1_MODE_MASK				BIT_MASK(5)
474
-#define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK			BIT_MASK(10)
486
+#define CM_CAMERRX_CTRL_CSI1_MODE_MASK				BIT(5)
487
+#define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK			BIT(10)
475488 #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK			GENMASK(12, 11)
476489 #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK			GENMASK(16, 13)
477
-#define CM_CAMERRX_CTRL_CSI0_MODE_MASK				BIT_MASK(17)
490
+#define CM_CAMERRX_CTRL_CSI0_MODE_MASK				BIT(17)
478491 
479492 #endif