.. | .. |
---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
---|
1 | 2 | /* |
---|
2 | 3 | * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores |
---|
3 | 4 | * |
---|
4 | 5 | * Integrated Consumer Infrared Controller |
---|
5 | 6 | * |
---|
6 | 7 | * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net> |
---|
7 | | - * |
---|
8 | | - * This program is free software; you can redistribute it and/or |
---|
9 | | - * modify it under the terms of the GNU General Public License |
---|
10 | | - * as published by the Free Software Foundation; either version 2 |
---|
11 | | - * of the License, or (at your option) any later version. |
---|
12 | | - * |
---|
13 | | - * This program is distributed in the hope that it will be useful, |
---|
14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
---|
16 | | - * GNU General Public License for more details. |
---|
17 | 8 | */ |
---|
18 | 9 | |
---|
19 | 10 | #include <linux/slab.h> |
---|
.. | .. |
---|
549 | 540 | ror = stats & STATS_ROR; /* Rx FIFO Over Run */ |
---|
550 | 541 | |
---|
551 | 542 | tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */ |
---|
552 | | - rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */ |
---|
| 543 | + rse = irqen & IRQEN_RSE; /* Rx FIFO Service Request IRQ Enable */ |
---|
553 | 544 | rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */ |
---|
554 | 545 | roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */ |
---|
555 | 546 | |
---|
.. | .. |
---|
638 | 629 | events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED; |
---|
639 | 630 | } |
---|
640 | 631 | if (v) { |
---|
641 | | - /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */ |
---|
| 632 | + /* Clear STATS_ROR & STATS_RTO as needed by resetting hardware */ |
---|
642 | 633 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v); |
---|
643 | 634 | cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl); |
---|
644 | 635 | *handled = true; |
---|
.. | .. |
---|
697 | 688 | } |
---|
698 | 689 | |
---|
699 | 690 | v = (unsigned) pulse_width_count_to_ns( |
---|
700 | | - (u16) (p->hw_fifo_data & FIFO_RXTX), divider); |
---|
| 691 | + (u16)(p->hw_fifo_data & FIFO_RXTX), divider) / 1000; |
---|
701 | 692 | if (v > IR_MAX_DURATION) |
---|
702 | 693 | v = IR_MAX_DURATION; |
---|
703 | 694 | |
---|
704 | | - init_ir_raw_event(&p->ir_core_data); |
---|
705 | | - p->ir_core_data.pulse = u; |
---|
706 | | - p->ir_core_data.duration = v; |
---|
707 | | - p->ir_core_data.timeout = w; |
---|
| 695 | + p->ir_core_data = (struct ir_raw_event) |
---|
| 696 | + { .pulse = u, .duration = v, .timeout = w }; |
---|
708 | 697 | |
---|
709 | 698 | v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s %s\n", |
---|
710 | 699 | v, u ? "mark" : "space", w ? "(timed out)" : ""); |
---|