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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/mailbox/imx-mailbox.c
..
..
@@ -4,27 +4,23 @@
4
4
  */
5
5
 
6
6
 #include <linux/clk.h>
7
+#include <linux/firmware/imx/ipc.h>
7
8
 #include <linux/interrupt.h>
8
9
 #include <linux/io.h>
10
+#include <linux/iopoll.h>
9
11
 #include <linux/kernel.h>
10
12
 #include <linux/mailbox_controller.h>
11
13
 #include <linux/module.h>
12
14
 #include <linux/of_device.h>
15
+#include <linux/pm_runtime.h>
16
+#include <linux/suspend.h>
13
17
 #include <linux/slab.h>
14
18
 
15
-/* Transmit Register */
16
-#define IMX_MU_xTRn(x)		(0x00 + 4 * (x))
17
-/* Receive Register */
18
-#define IMX_MU_xRRn(x)		(0x10 + 4 * (x))
19
-/* Status Register */
20
-#define IMX_MU_xSR		0x20
21
19
 #define IMX_MU_xSR_GIPn(x)	BIT(28 + (3 - (x)))
22
20
 #define IMX_MU_xSR_RFn(x)	BIT(24 + (3 - (x)))
23
21
 #define IMX_MU_xSR_TEn(x)	BIT(20 + (3 - (x)))
24
22
 #define IMX_MU_xSR_BRDIP	BIT(9)
25
23
 
26
-/* Control Register */
27
-#define IMX_MU_xCR		0x24
28
24
 /* General Purpose Interrupt Enable */
29
25
 #define IMX_MU_xCR_GIEn(x)	BIT(28 + (3 - (x)))
30
26
 /* Receive Interrupt Enable */
..
..
@@ -35,6 +31,8 @@
35
31
 #define IMX_MU_xCR_GIRn(x)	BIT(16 + (3 - (x)))
36
32
 
37
33
 #define IMX_MU_CHANS		16
34
+/* TX0/RX0/RXDB[0-3] */
35
+#define IMX_MU_SCU_CHANS	6
38
36
 #define IMX_MU_CHAN_NAME_SIZE	20
39
37
 
40
38
 enum imx_mu_chan_type {
..
..
@@ -42,6 +40,11 @@
42
40
 	IMX_MU_TYPE_RX,		/* Rx */
43
41
 	IMX_MU_TYPE_TXDB,	/* Tx doorbell */
44
42
 	IMX_MU_TYPE_RXDB,	/* Rx doorbell */
43
+};
44
+
45
+struct imx_sc_rpc_msg_max {
46
+	struct imx_sc_rpc_msg hdr;
47
+	u32 data[7];
45
48
 };
46
49
 
47
50
 struct imx_mu_con_priv {
..
..
@@ -61,10 +64,24 @@
61
64
 	struct mbox_chan	mbox_chans[IMX_MU_CHANS];
62
65
 
63
66
 	struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
67
+	const struct imx_mu_dcfg	*dcfg;
64
68
 	struct clk		*clk;
65
69
 	int			irq;
70
+	bool			suspend;
71
+
72
+	u32 xcr;
66
73
 
67
74
 	bool			side_b;
75
+};
76
+
77
+struct imx_mu_dcfg {
78
+	int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
79
+	int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
80
+	void (*init)(struct imx_mu_priv *priv);
81
+	u32	xTR[4];		/* Transmit Registers */
82
+	u32	xRR[4];		/* Receive Registers */
83
+	u32	xSR;		/* Status Register */
84
+	u32	xCR;		/* Control Register */
68
85
 };
69
86
 
70
87
 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
..
..
@@ -88,13 +105,128 @@
88
105
 	u32 val;
89
106
 
90
107
 	spin_lock_irqsave(&priv->xcr_lock, flags);
91
-	val = imx_mu_read(priv, IMX_MU_xCR);
108
+	val = imx_mu_read(priv, priv->dcfg->xCR);
92
109
 	val &= ~clr;
93
110
 	val |= set;
94
-	imx_mu_write(priv, val, IMX_MU_xCR);
111
+	imx_mu_write(priv, val, priv->dcfg->xCR);
95
112
 	spin_unlock_irqrestore(&priv->xcr_lock, flags);
96
113
 
97
114
 	return val;
115
+}
116
+
117
+static int imx_mu_generic_tx(struct imx_mu_priv *priv,
118
+			     struct imx_mu_con_priv *cp,
119
+			     void *data)
120
+{
121
+	u32 *arg = data;
122
+
123
+	switch (cp->type) {
124
+	case IMX_MU_TYPE_TX:
125
+		imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
126
+		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
127
+		break;
128
+	case IMX_MU_TYPE_TXDB:
129
+		imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
130
+		tasklet_schedule(&cp->txdb_tasklet);
131
+		break;
132
+	default:
133
+		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
134
+		return -EINVAL;
135
+	}
136
+
137
+	return 0;
138
+}
139
+
140
+static int imx_mu_generic_rx(struct imx_mu_priv *priv,
141
+			     struct imx_mu_con_priv *cp)
142
+{
143
+	u32 dat;
144
+
145
+	dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
146
+	mbox_chan_received_data(cp->chan, (void *)&dat);
147
+
148
+	return 0;
149
+}
150
+
151
+static int imx_mu_scu_tx(struct imx_mu_priv *priv,
152
+			 struct imx_mu_con_priv *cp,
153
+			 void *data)
154
+{
155
+	struct imx_sc_rpc_msg_max *msg = data;
156
+	u32 *arg = data;
157
+	int i, ret;
158
+	u32 xsr;
159
+
160
+	switch (cp->type) {
161
+	case IMX_MU_TYPE_TX:
162
+		/*
163
+		 * msg->hdr.size specifies the number of u32 words while
164
+		 * sizeof yields bytes.
165
+		 */
166
+
167
+		if (msg->hdr.size > sizeof(*msg) / 4) {
168
+			/*
169
+			 * The real message size can be different to
170
+			 * struct imx_sc_rpc_msg_max size
171
+			 */
172
+			dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
173
+			return -EINVAL;
174
+		}
175
+
176
+		for (i = 0; i < 4 && i < msg->hdr.size; i++)
177
+			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
178
+		for (; i < msg->hdr.size; i++) {
179
+			ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
180
+						 xsr,
181
+						 xsr & IMX_MU_xSR_TEn(i % 4),
182
+						 0, 100);
183
+			if (ret) {
184
+				dev_err(priv->dev, "Send data index: %d timeout\n", i);
185
+				return ret;
186
+			}
187
+			imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
188
+		}
189
+
190
+		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
191
+		break;
192
+	default:
193
+		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
194
+		return -EINVAL;
195
+	}
196
+
197
+	return 0;
198
+}
199
+
200
+static int imx_mu_scu_rx(struct imx_mu_priv *priv,
201
+			 struct imx_mu_con_priv *cp)
202
+{
203
+	struct imx_sc_rpc_msg_max msg;
204
+	u32 *data = (u32 *)&msg;
205
+	int i, ret;
206
+	u32 xsr;
207
+
208
+	imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
209
+	*data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
210
+
211
+	if (msg.hdr.size > sizeof(msg) / 4) {
212
+		dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
213
+		return -EINVAL;
214
+	}
215
+
216
+	for (i = 1; i < msg.hdr.size; i++) {
217
+		ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
218
+					 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
219
+		if (ret) {
220
+			dev_err(priv->dev, "timeout read idx %d\n", i);
221
+			return ret;
222
+		}
223
+		*data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
224
+	}
225
+
226
+	imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
227
+	mbox_chan_received_data(cp->chan, (void *)&msg);
228
+
229
+	return 0;
98
230
 }
99
231
 
100
232
 static void imx_mu_txdb_tasklet(unsigned long data)
..
..
@@ -109,10 +241,10 @@
109
241
 	struct mbox_chan *chan = p;
110
242
 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
111
243
 	struct imx_mu_con_priv *cp = chan->con_priv;
112
-	u32 val, ctrl, dat;
244
+	u32 val, ctrl;
113
245
 
114
-	ctrl = imx_mu_read(priv, IMX_MU_xCR);
115
-	val = imx_mu_read(priv, IMX_MU_xSR);
246
+	ctrl = imx_mu_read(priv, priv->dcfg->xCR);
247
+	val = imx_mu_read(priv, priv->dcfg->xSR);
116
248
 
117
249
 	switch (cp->type) {
118
250
 	case IMX_MU_TYPE_TX:
..
..
@@ -138,15 +270,17 @@
138
270
 		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
139
271
 		mbox_chan_txdone(chan, 0);
140
272
 	} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
141
-		dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
142
-		mbox_chan_received_data(chan, (void *)&dat);
273
+		priv->dcfg->rx(priv, cp);
143
274
 	} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
144
-		imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
275
+		imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
145
276
 		mbox_chan_received_data(chan, NULL);
146
277
 	} else {
147
278
 		dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
148
279
 		return IRQ_NONE;
149
280
 	}
281
+
282
+	if (priv->suspend)
283
+		pm_system_wakeup();
150
284
 
151
285
 	return IRQ_HANDLED;
152
286
 }
..
..
@@ -155,31 +289,18 @@
155
289
 {
156
290
 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
157
291
 	struct imx_mu_con_priv *cp = chan->con_priv;
158
-	u32 *arg = data;
159
292
 
160
-	switch (cp->type) {
161
-	case IMX_MU_TYPE_TX:
162
-		imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
163
-		imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
164
-		break;
165
-	case IMX_MU_TYPE_TXDB:
166
-		imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
167
-		tasklet_schedule(&cp->txdb_tasklet);
168
-		break;
169
-	default:
170
-		dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
171
-		return -EINVAL;
172
-	}
173
-
174
-	return 0;
293
+	return priv->dcfg->tx(priv, cp, data);
175
294
 }
176
295
 
177
296
 static int imx_mu_startup(struct mbox_chan *chan)
178
297
 {
179
298
 	struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
180
299
 	struct imx_mu_con_priv *cp = chan->con_priv;
300
+	unsigned long irq_flag = IRQF_SHARED;
181
301
 	int ret;
182
302
 
303
+	pm_runtime_get_sync(priv->dev);
183
304
 	if (cp->type == IMX_MU_TYPE_TXDB) {
184
305
 		/* Tx doorbell don't have ACK support */
185
306
 		tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
..
..
@@ -187,8 +308,12 @@
187
308
 		return 0;
188
309
 	}
189
310
 
190
-	ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED, cp->irq_desc,
191
-			  chan);
311
+	/* IPC MU should be with IRQF_NO_SUSPEND set */
312
+	if (!priv->dev->pm_domain)
313
+		irq_flag |= IRQF_NO_SUSPEND;
314
+
315
+	ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
316
+			  cp->irq_desc, chan);
192
317
 	if (ret) {
193
318
 		dev_err(priv->dev,
194
319
 			"Unable to acquire IRQ %d\n", priv->irq);
..
..
@@ -206,6 +331,8 @@
206
331
 		break;
207
332
 	}
208
333
 
334
+	priv->suspend = true;
335
+
209
336
 	return 0;
210
337
 }
211
338
 
..
..
@@ -216,13 +343,26 @@
216
343
 
217
344
 	if (cp->type == IMX_MU_TYPE_TXDB) {
218
345
 		tasklet_kill(&cp->txdb_tasklet);
346
+		pm_runtime_put_sync(priv->dev);
219
347
 		return;
220
348
 	}
221
349
 
222
-	imx_mu_xcr_rmw(priv, 0,
223
-		   IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx));
350
+	switch (cp->type) {
351
+	case IMX_MU_TYPE_TX:
352
+		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
353
+		break;
354
+	case IMX_MU_TYPE_RX:
355
+		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
356
+		break;
357
+	case IMX_MU_TYPE_RXDB:
358
+		imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
359
+		break;
360
+	default:
361
+		break;
362
+	}
224
363
 
225
364
 	free_irq(priv->irq, chan);
365
+	pm_runtime_put_sync(priv->dev);
226
366
 }
227
367
 
228
368
 static const struct mbox_chan_ops imx_mu_ops = {
..
..
@@ -230,6 +370,42 @@
230
370
 	.startup = imx_mu_startup,
231
371
 	.shutdown = imx_mu_shutdown,
232
372
 };
373
+
374
+static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
375
+					  const struct of_phandle_args *sp)
376
+{
377
+	u32 type, idx, chan;
378
+
379
+	if (sp->args_count != 2) {
380
+		dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
381
+		return ERR_PTR(-EINVAL);
382
+	}
383
+
384
+	type = sp->args[0]; /* channel type */
385
+	idx = sp->args[1]; /* index */
386
+
387
+	switch (type) {
388
+	case IMX_MU_TYPE_TX:
389
+	case IMX_MU_TYPE_RX:
390
+		if (idx != 0)
391
+			dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
392
+		chan = type;
393
+		break;
394
+	case IMX_MU_TYPE_RXDB:
395
+		chan = 2 + idx;
396
+		break;
397
+	default:
398
+		dev_err(mbox->dev, "Invalid chan type: %d\n", type);
399
+		return ERR_PTR(-EINVAL);
400
+	}
401
+
402
+	if (chan >= mbox->num_chans) {
403
+		dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
404
+		return ERR_PTR(-EINVAL);
405
+	}
406
+
407
+	return &mbox->chans[chan];
408
+}
233
409
 
234
410
 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
235
411
 				       const struct of_phandle_args *sp)
..
..
@@ -255,20 +431,57 @@
255
431
 
256
432
 static void imx_mu_init_generic(struct imx_mu_priv *priv)
257
433
 {
434
+	unsigned int i;
435
+
436
+	for (i = 0; i < IMX_MU_CHANS; i++) {
437
+		struct imx_mu_con_priv *cp = &priv->con_priv[i];
438
+
439
+		cp->idx = i % 4;
440
+		cp->type = i >> 2;
441
+		cp->chan = &priv->mbox_chans[i];
442
+		priv->mbox_chans[i].con_priv = cp;
443
+		snprintf(cp->irq_desc, sizeof(cp->irq_desc),
444
+			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
445
+	}
446
+
447
+	priv->mbox.num_chans = IMX_MU_CHANS;
448
+	priv->mbox.of_xlate = imx_mu_xlate;
449
+
258
450
 	if (priv->side_b)
259
451
 		return;
260
452
 
261
453
 	/* Set default MU configuration */
262
-	imx_mu_write(priv, 0, IMX_MU_xCR);
454
+	imx_mu_write(priv, 0, priv->dcfg->xCR);
455
+}
456
+
457
+static void imx_mu_init_scu(struct imx_mu_priv *priv)
458
+{
459
+	unsigned int i;
460
+
461
+	for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
462
+		struct imx_mu_con_priv *cp = &priv->con_priv[i];
463
+
464
+		cp->idx = i < 2 ? 0 : i - 2;
465
+		cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
466
+		cp->chan = &priv->mbox_chans[i];
467
+		priv->mbox_chans[i].con_priv = cp;
468
+		snprintf(cp->irq_desc, sizeof(cp->irq_desc),
469
+			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
470
+	}
471
+
472
+	priv->mbox.num_chans = IMX_MU_SCU_CHANS;
473
+	priv->mbox.of_xlate = imx_mu_scu_xlate;
474
+
475
+	/* Set default MU configuration */
476
+	imx_mu_write(priv, 0, priv->dcfg->xCR);
263
477
 }
264
478
 
265
479
 static int imx_mu_probe(struct platform_device *pdev)
266
480
 {
267
481
 	struct device *dev = &pdev->dev;
268
482
 	struct device_node *np = dev->of_node;
269
-	struct resource *iomem;
270
483
 	struct imx_mu_priv *priv;
271
-	unsigned int i;
484
+	const struct imx_mu_dcfg *dcfg;
272
485
 	int ret;
273
486
 
274
487
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
..
..
@@ -277,14 +490,18 @@
277
490
 
278
491
 	priv->dev = dev;
279
492
 
280
-	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
281
-	priv->base = devm_ioremap_resource(&pdev->dev, iomem);
493
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
282
494
 	if (IS_ERR(priv->base))
283
495
 		return PTR_ERR(priv->base);
284
496
 
285
497
 	priv->irq = platform_get_irq(pdev, 0);
286
498
 	if (priv->irq < 0)
287
499
 		return priv->irq;
500
+
501
+	dcfg = of_device_get_match_data(dev);
502
+	if (!dcfg)
503
+		return -EINVAL;
504
+	priv->dcfg = dcfg;
288
505
 
289
506
 	priv->clk = devm_clk_get(dev, NULL);
290
507
 	if (IS_ERR(priv->clk)) {
..
..
@@ -300,50 +517,151 @@
300
517
 		return ret;
301
518
 	}
302
519
 
303
-	for (i = 0; i < IMX_MU_CHANS; i++) {
304
-		struct imx_mu_con_priv *cp = &priv->con_priv[i];
305
-
306
-		cp->idx = i % 4;
307
-		cp->type = i >> 2;
308
-		cp->chan = &priv->mbox_chans[i];
309
-		priv->mbox_chans[i].con_priv = cp;
310
-		snprintf(cp->irq_desc, sizeof(cp->irq_desc),
311
-			 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
312
-	}
313
-
314
520
 	priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
521
+
522
+	priv->dcfg->init(priv);
315
523
 
316
524
 	spin_lock_init(&priv->xcr_lock);
317
525
 
318
526
 	priv->mbox.dev = dev;
319
527
 	priv->mbox.ops = &imx_mu_ops;
320
528
 	priv->mbox.chans = priv->mbox_chans;
321
-	priv->mbox.num_chans = IMX_MU_CHANS;
322
-	priv->mbox.of_xlate = imx_mu_xlate;
323
529
 	priv->mbox.txdone_irq = true;
324
530
 
325
531
 	platform_set_drvdata(pdev, priv);
326
532
 
327
-	imx_mu_init_generic(priv);
533
+	ret = devm_mbox_controller_register(dev, &priv->mbox);
534
+	if (ret) {
535
+		clk_disable_unprepare(priv->clk);
536
+		return ret;
537
+	}
328
538
 
329
-	return mbox_controller_register(&priv->mbox);
539
+	pm_runtime_enable(dev);
540
+
541
+	ret = pm_runtime_get_sync(dev);
542
+	if (ret < 0) {
543
+		pm_runtime_put_noidle(dev);
544
+		goto disable_runtime_pm;
545
+	}
546
+
547
+	ret = pm_runtime_put_sync(dev);
548
+	if (ret < 0)
549
+		goto disable_runtime_pm;
550
+
551
+	clk_disable_unprepare(priv->clk);
552
+
553
+	priv->suspend = false;
554
+
555
+	return 0;
556
+
557
+disable_runtime_pm:
558
+	pm_runtime_disable(dev);
559
+	clk_disable_unprepare(priv->clk);
560
+	return ret;
330
561
 }
331
562
 
332
563
 static int imx_mu_remove(struct platform_device *pdev)
333
564
 {
334
565
 	struct imx_mu_priv *priv = platform_get_drvdata(pdev);
335
566
 
336
-	mbox_controller_unregister(&priv->mbox);
567
+	pm_runtime_disable(priv->dev);
568
+
569
+	return 0;
570
+}
571
+
572
+static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
573
+	.tx	= imx_mu_generic_tx,
574
+	.rx	= imx_mu_generic_rx,
575
+	.init	= imx_mu_init_generic,
576
+	.xTR	= {0x0, 0x4, 0x8, 0xc},
577
+	.xRR	= {0x10, 0x14, 0x18, 0x1c},
578
+	.xSR	= 0x20,
579
+	.xCR	= 0x24,
580
+};
581
+
582
+static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
583
+	.tx	= imx_mu_generic_tx,
584
+	.rx	= imx_mu_generic_rx,
585
+	.init	= imx_mu_init_generic,
586
+	.xTR	= {0x20, 0x24, 0x28, 0x2c},
587
+	.xRR	= {0x40, 0x44, 0x48, 0x4c},
588
+	.xSR	= 0x60,
589
+	.xCR	= 0x64,
590
+};
591
+
592
+static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
593
+	.tx	= imx_mu_scu_tx,
594
+	.rx	= imx_mu_scu_rx,
595
+	.init	= imx_mu_init_scu,
596
+	.xTR	= {0x0, 0x4, 0x8, 0xc},
597
+	.xRR	= {0x10, 0x14, 0x18, 0x1c},
598
+	.xSR	= 0x20,
599
+	.xCR	= 0x24,
600
+};
601
+
602
+static const struct of_device_id imx_mu_dt_ids[] = {
603
+	{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
604
+	{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
605
+	{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
606
+	{ },
607
+};
608
+MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
609
+
610
+static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
611
+{
612
+	struct imx_mu_priv *priv = dev_get_drvdata(dev);
613
+
614
+	if (!priv->clk)
615
+		priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
616
+
617
+	return 0;
618
+}
619
+
620
+static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
621
+{
622
+	struct imx_mu_priv *priv = dev_get_drvdata(dev);
623
+
624
+	/*
625
+	 * ONLY restore MU when context lost, the TIE could
626
+	 * be set during noirq resume as there is MU data
627
+	 * communication going on, and restore the saved
628
+	 * value will overwrite the TIE and cause MU data
629
+	 * send failed, may lead to system freeze. This issue
630
+	 * is observed by testing freeze mode suspend.
631
+	 */
632
+	if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
633
+		imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
634
+
635
+	return 0;
636
+}
637
+
638
+static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
639
+{
640
+	struct imx_mu_priv *priv = dev_get_drvdata(dev);
641
+
337
642
 	clk_disable_unprepare(priv->clk);
338
643
 
339
644
 	return 0;
340
645
 }
341
646
 
342
-static const struct of_device_id imx_mu_dt_ids[] = {
343
-	{ .compatible = "fsl,imx6sx-mu" },
344
-	{ },
647
+static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
648
+{
649
+	struct imx_mu_priv *priv = dev_get_drvdata(dev);
650
+	int ret;
651
+
652
+	ret = clk_prepare_enable(priv->clk);
653
+	if (ret)
654
+		dev_err(dev, "failed to enable clock\n");
655
+
656
+	return ret;
657
+}
658
+
659
+static const struct dev_pm_ops imx_mu_pm_ops = {
660
+	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
661
+				      imx_mu_resume_noirq)
662
+	SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
663
+			   imx_mu_runtime_resume, NULL)
345
664
 };
346
-MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
347
665
 
348
666
 static struct platform_driver imx_mu_driver = {
349
667
 	.probe		= imx_mu_probe,
..
..
@@ -351,6 +669,7 @@
351
669
 	.driver = {
352
670
 		.name	= "imx_mu",
353
671
 		.of_match_table = imx_mu_dt_ids,
672
+		.pm = &imx_mu_pm_ops,
354
673
 	},
355
674
 };
356
675
 module_platform_driver(imx_mu_driver);