hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c
kernel/drivers/iommu/mtk_iommu.h
....@@ -1,15 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23 * Copyright (c) 2015-2016 MediaTek Inc.
34 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
- * GNU General Public License for more details.
135 */
146
157 #ifndef _MTK_IOMMU_H_
....@@ -23,21 +15,49 @@
2315 #include <linux/iommu.h>
2416 #include <linux/list.h>
2517 #include <linux/spinlock.h>
18
+#include <linux/dma-mapping.h>
2619 #include <soc/mediatek/smi.h>
20
+#include <dt-bindings/memory/mtk-memory-port.h>
21
+
22
+#define MTK_LARB_COM_MAX 8
23
+#define MTK_LARB_SUBCOM_MAX 4
24
+
25
+#define MTK_IOMMU_GROUP_MAX 8
2726
2827 struct mtk_iommu_suspend_reg {
29
- u32 standard_axi_mode;
28
+ union {
29
+ u32 standard_axi_mode;/* v1 */
30
+ u32 misc_ctrl;/* v2 */
31
+ };
3032 u32 dcm_dis;
3133 u32 ctrl_reg;
3234 u32 int_control0;
3335 u32 int_main_control;
3436 u32 ivrp_paddr;
37
+ u32 vld_pa_rng;
38
+ u32 wr_len_ctrl;
3539 };
3640
3741 enum mtk_iommu_plat {
3842 M4U_MT2701,
3943 M4U_MT2712,
44
+ M4U_MT6779,
45
+ M4U_MT8167,
4046 M4U_MT8173,
47
+ M4U_MT8183,
48
+ M4U_MT8192,
49
+};
50
+
51
+struct mtk_iommu_iova_region;
52
+
53
+struct mtk_iommu_plat_data {
54
+ enum mtk_iommu_plat m4u_plat;
55
+ u32 flags;
56
+ u32 inv_sel_reg;
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+
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+ unsigned int iova_region_nr;
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+ const struct mtk_iommu_iova_region *iova_region;
60
+ unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
4161 };
4262
4363 struct mtk_iommu_domain;
....@@ -50,15 +70,20 @@
5070 phys_addr_t protect_base; /* protect memory base */
5171 struct mtk_iommu_suspend_reg reg;
5272 struct mtk_iommu_domain *m4u_dom;
53
- struct iommu_group *m4u_group;
54
- struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
73
+ struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX];
5574 bool enable_4GB;
56
- bool tlb_flush_active;
75
+ spinlock_t tlb_lock; /* lock for tlb range flush */
5776
5877 struct iommu_device iommu;
59
- enum mtk_iommu_plat m4u_plat;
78
+ const struct mtk_iommu_plat_data *plat_data;
79
+ struct device *smicomm_dev;
80
+
81
+ struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */
82
+
83
+ struct mutex mutex; /* Protect m4u_group/m4u_dom above */
6084
6185 struct list_head list;
86
+ struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX];
6287 };
6388
6489 static inline int compare_of(struct device *dev, void *data)
....@@ -75,14 +100,14 @@
75100 {
76101 struct mtk_iommu_data *data = dev_get_drvdata(dev);
77102
78
- return component_bind_all(dev, &data->smi_imu);
103
+ return component_bind_all(dev, &data->larb_imu);
79104 }
80105
81106 static inline void mtk_iommu_unbind(struct device *dev)
82107 {
83108 struct mtk_iommu_data *data = dev_get_drvdata(dev);
84109
85
- component_unbind_all(dev, &data->smi_imu);
110
+ component_unbind_all(dev, &data->larb_imu);
86111 }
87112
88113 #endif