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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/iio/adc/sc27xx_adc.c
..
..
@@ -3,12 +3,13 @@
3
3
 
4
4
 #include <linux/hwspinlock.h>
5
5
 #include <linux/iio/iio.h>
6
-#include <linux/interrupt.h>
7
6
 #include <linux/module.h>
7
+#include <linux/nvmem-consumer.h>
8
8
 #include <linux/of.h>
9
9
 #include <linux/of_device.h>
10
10
 #include <linux/platform_device.h>
11
11
 #include <linux/regmap.h>
12
+#include <linux/slab.h>
12
13
 
13
14
 /* PMIC global registers definition */
14
15
 #define SC27XX_MODULE_EN		0xc08
..
..
@@ -35,8 +36,8 @@
35
36
 
36
37
 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
37
38
 #define SC27XX_ADC_CHN_ID_MASK		GENMASK(4, 0)
38
-#define SC27XX_ADC_SCALE_MASK		GENMASK(10, 8)
39
-#define SC27XX_ADC_SCALE_SHIFT		8
39
+#define SC27XX_ADC_SCALE_MASK		GENMASK(10, 9)
40
+#define SC27XX_ADC_SCALE_SHIFT		9
40
41
 
41
42
 /* Bits definitions for SC27XX_ADC_INT_EN registers */
42
43
 #define SC27XX_ADC_IRQ_EN		BIT(0)
..
..
@@ -44,11 +45,18 @@
44
45
 /* Bits definitions for SC27XX_ADC_INT_CLR registers */
45
46
 #define SC27XX_ADC_IRQ_CLR		BIT(0)
46
47
 
48
+/* Bits definitions for SC27XX_ADC_INT_RAW registers */
49
+#define SC27XX_ADC_IRQ_RAW		BIT(0)
50
+
47
51
 /* Mask definition for SC27XX_ADC_DATA register */
48
52
 #define SC27XX_ADC_DATA_MASK		GENMASK(11, 0)
49
53
 
50
54
 /* Timeout (ms) for the trylock of hardware spinlocks */
51
55
 #define SC27XX_ADC_HWLOCK_TIMEOUT	5000
56
+
57
+/* Timeout (us) for ADC data conversion according to ADC datasheet */
58
+#define SC27XX_ADC_RDY_TIMEOUT		1000000
59
+#define SC27XX_ADC_POLL_RAW_STATUS	500
52
60
 
53
61
 /* Maximum ADC channel number */
54
62
 #define SC27XX_ADC_CHANNEL_MAX		32
..
..
@@ -67,10 +75,8 @@
67
75
 	 * subsystems which will access the unique ADC controller.
68
76
 	 */
69
77
 	struct hwspinlock *hwlock;
70
-	struct completion completion;
71
78
 	int channel_scale[SC27XX_ADC_CHANNEL_MAX];
72
79
 	u32 base;
73
-	int value;
74
80
 	int irq;
75
81
 };
76
82
 
..
..
@@ -87,15 +93,72 @@
87
93
  * should use the small-scale graph, and if more than 1.2v, we should use the
88
94
  * big-scale graph.
89
95
  */
90
-static const struct sc27xx_adc_linear_graph big_scale_graph = {
96
+static struct sc27xx_adc_linear_graph big_scale_graph = {
91
97
 	4200, 3310,
92
98
 	3600, 2832,
93
99
 };
94
100
 
95
-static const struct sc27xx_adc_linear_graph small_scale_graph = {
101
+static struct sc27xx_adc_linear_graph small_scale_graph = {
96
102
 	1000, 3413,
97
103
 	100, 341,
98
104
 };
105
+
106
+static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = {
107
+	4200, 850,
108
+	3600, 728,
109
+};
110
+
111
+static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = {
112
+	1000, 838,
113
+	100, 84,
114
+};
115
+
116
+static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
117
+{
118
+	return ((calib_data & 0xff) + calib_adc - 128) * 4;
119
+}
120
+
121
+static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
122
+					bool big_scale)
123
+{
124
+	const struct sc27xx_adc_linear_graph *calib_graph;
125
+	struct sc27xx_adc_linear_graph *graph;
126
+	struct nvmem_cell *cell;
127
+	const char *cell_name;
128
+	u32 calib_data = 0;
129
+	void *buf;
130
+	size_t len;
131
+
132
+	if (big_scale) {
133
+		calib_graph = &sc2731_big_scale_graph_calib;
134
+		graph = &big_scale_graph;
135
+		cell_name = "big_scale_calib";
136
+	} else {
137
+		calib_graph = &sc2731_small_scale_graph_calib;
138
+		graph = &small_scale_graph;
139
+		cell_name = "small_scale_calib";
140
+	}
141
+
142
+	cell = nvmem_cell_get(data->dev, cell_name);
143
+	if (IS_ERR(cell))
144
+		return PTR_ERR(cell);
145
+
146
+	buf = nvmem_cell_read(cell, &len);
147
+	nvmem_cell_put(cell);
148
+
149
+	if (IS_ERR(buf))
150
+		return PTR_ERR(buf);
151
+
152
+	memcpy(&calib_data, buf, min(len, sizeof(u32)));
153
+
154
+	/* Only need to calibrate the adc values in the linear graph. */
155
+	graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
156
+	graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
157
+						calib_graph->adc1);
158
+
159
+	kfree(buf);
160
+	return 0;
161
+}
99
162
 
100
163
 static int sc27xx_adc_get_ratio(int channel, int scale)
101
164
 {
..
..
@@ -126,9 +189,7 @@
126
189
 			   int scale, int *val)
127
190
 {
128
191
 	int ret;
129
-	u32 tmp;
130
-
131
-	reinit_completion(&data->completion);
192
+	u32 tmp, value, status;
132
193
 
133
194
 	ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
134
195
 	if (ret) {
..
..
@@ -140,6 +201,11 @@
140
201
 				 SC27XX_ADC_EN, SC27XX_ADC_EN);
141
202
 	if (ret)
142
203
 		goto unlock_adc;
204
+
205
+	ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
206
+				 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
207
+	if (ret)
208
+		goto disable_adc;
143
209
 
144
210
 	/* Configure the channel id and scale */
145
211
 	tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK;
..
..
@@ -164,7 +230,21 @@
164
230
 	if (ret)
165
231
 		goto disable_adc;
166
232
 
167
-	wait_for_completion(&data->completion);
233
+	ret = regmap_read_poll_timeout(data->regmap,
234
+				       data->base + SC27XX_ADC_INT_RAW,
235
+				       status, (status & SC27XX_ADC_IRQ_RAW),
236
+				       SC27XX_ADC_POLL_RAW_STATUS,
237
+				       SC27XX_ADC_RDY_TIMEOUT);
238
+	if (ret) {
239
+		dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
240
+		goto disable_adc;
241
+	}
242
+
243
+	ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
244
+	if (ret)
245
+		goto disable_adc;
246
+
247
+	value &= SC27XX_ADC_DATA_MASK;
168
248
 
169
249
 disable_adc:
170
250
 	regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
..
..
@@ -173,30 +253,9 @@
173
253
 	hwspin_unlock_raw(data->hwlock);
174
254
 
175
255
 	if (!ret)
176
-		*val = data->value;
256
+		*val = value;
177
257
 
178
258
 	return ret;
179
-}
180
-
181
-static irqreturn_t sc27xx_adc_isr(int irq, void *dev_id)
182
-{
183
-	struct sc27xx_adc_data *data = dev_id;
184
-	int ret;
185
-
186
-	ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
187
-				 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
188
-	if (ret)
189
-		return IRQ_RETVAL(ret);
190
-
191
-	ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA,
192
-			  &data->value);
193
-	if (ret)
194
-		return IRQ_RETVAL(ret);
195
-
196
-	data->value &= SC27XX_ADC_DATA_MASK;
197
-	complete(&data->completion);
198
-
199
-	return IRQ_HANDLED;
200
259
 }
201
260
 
202
261
 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
..
..
@@ -209,7 +268,7 @@
209
268
 	*div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
210
269
 }
211
270
 
212
-static int sc27xx_adc_to_volt(const struct sc27xx_adc_linear_graph *graph,
271
+static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
213
272
 			      int raw_adc)
214
273
 {
215
274
 	int tmp;
..
..
@@ -273,6 +332,17 @@
273
332
 	int ret, tmp;
274
333
 
275
334
 	switch (mask) {
335
+	case IIO_CHAN_INFO_RAW:
336
+		mutex_lock(&indio_dev->mlock);
337
+		ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
338
+		mutex_unlock(&indio_dev->mlock);
339
+
340
+		if (ret)
341
+			return ret;
342
+
343
+		*val = tmp;
344
+		return IIO_VAL_INT;
345
+
276
346
 	case IIO_CHAN_INFO_PROCESSED:
277
347
 		mutex_lock(&indio_dev->mlock);
278
348
 		ret = sc27xx_adc_read_processed(data, chan->channel, scale,
..
..
@@ -315,48 +385,47 @@
315
385
 	.write_raw = &sc27xx_adc_write_raw,
316
386
 };
317
387
 
318
-#define SC27XX_ADC_CHANNEL(index) {				\
388
+#define SC27XX_ADC_CHANNEL(index, mask) {			\
319
389
 	.type = IIO_VOLTAGE,					\
320
390
 	.channel = index,					\
321
-	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |	\
322
-			      BIT(IIO_CHAN_INFO_SCALE),		\
391
+	.info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE),	\
323
392
 	.datasheet_name = "CH##index",				\
324
393
 	.indexed = 1,						\
325
394
 }
326
395
 
327
396
 static const struct iio_chan_spec sc27xx_channels[] = {
328
-	SC27XX_ADC_CHANNEL(0),
329
-	SC27XX_ADC_CHANNEL(1),
330
-	SC27XX_ADC_CHANNEL(2),
331
-	SC27XX_ADC_CHANNEL(3),
332
-	SC27XX_ADC_CHANNEL(4),
333
-	SC27XX_ADC_CHANNEL(5),
334
-	SC27XX_ADC_CHANNEL(6),
335
-	SC27XX_ADC_CHANNEL(7),
336
-	SC27XX_ADC_CHANNEL(8),
337
-	SC27XX_ADC_CHANNEL(9),
338
-	SC27XX_ADC_CHANNEL(10),
339
-	SC27XX_ADC_CHANNEL(11),
340
-	SC27XX_ADC_CHANNEL(12),
341
-	SC27XX_ADC_CHANNEL(13),
342
-	SC27XX_ADC_CHANNEL(14),
343
-	SC27XX_ADC_CHANNEL(15),
344
-	SC27XX_ADC_CHANNEL(16),
345
-	SC27XX_ADC_CHANNEL(17),
346
-	SC27XX_ADC_CHANNEL(18),
347
-	SC27XX_ADC_CHANNEL(19),
348
-	SC27XX_ADC_CHANNEL(20),
349
-	SC27XX_ADC_CHANNEL(21),
350
-	SC27XX_ADC_CHANNEL(22),
351
-	SC27XX_ADC_CHANNEL(23),
352
-	SC27XX_ADC_CHANNEL(24),
353
-	SC27XX_ADC_CHANNEL(25),
354
-	SC27XX_ADC_CHANNEL(26),
355
-	SC27XX_ADC_CHANNEL(27),
356
-	SC27XX_ADC_CHANNEL(28),
357
-	SC27XX_ADC_CHANNEL(29),
358
-	SC27XX_ADC_CHANNEL(30),
359
-	SC27XX_ADC_CHANNEL(31),
397
+	SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
398
+	SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
399
+	SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
400
+	SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
401
+	SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
402
+	SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
403
+	SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
404
+	SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
405
+	SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
406
+	SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
407
+	SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
408
+	SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
409
+	SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
410
+	SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
411
+	SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
412
+	SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
413
+	SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
414
+	SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
415
+	SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
416
+	SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
417
+	SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
418
+	SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
419
+	SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
420
+	SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
421
+	SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
422
+	SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
423
+	SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
424
+	SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
425
+	SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
426
+	SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
427
+	SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
428
+	SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
360
429
 };
361
430
 
362
431
 static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
..
..
@@ -375,8 +444,12 @@
375
444
 	if (ret)
376
445
 		goto disable_adc;
377
446
 
378
-	ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN,
379
-				 SC27XX_ADC_IRQ_EN, SC27XX_ADC_IRQ_EN);
447
+	/* ADC channel scales' calibration from nvmem device */
448
+	ret = sc27xx_adc_scale_calibration(data, true);
449
+	if (ret)
450
+		goto disable_clk;
451
+
452
+	ret = sc27xx_adc_scale_calibration(data, false);
380
453
 	if (ret)
381
454
 		goto disable_clk;
382
455
 
..
..
@@ -396,9 +469,6 @@
396
469
 {
397
470
 	struct sc27xx_adc_data *data = _data;
398
471
 
399
-	regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN,
400
-			   SC27XX_ADC_IRQ_EN, 0);
401
-
402
472
 	/* Disable ADC work clock and controller clock */
403
473
 	regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
404
474
 			   SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
..
..
@@ -407,97 +477,70 @@
407
477
 			   SC27XX_MODULE_ADC_EN, 0);
408
478
 }
409
479
 
410
-static void sc27xx_adc_free_hwlock(void *_data)
411
-{
412
-	struct hwspinlock *hwlock = _data;
413
-
414
-	hwspin_lock_free(hwlock);
415
-}
416
-
417
480
 static int sc27xx_adc_probe(struct platform_device *pdev)
418
481
 {
419
-	struct device_node *np = pdev->dev.of_node;
482
+	struct device *dev = &pdev->dev;
483
+	struct device_node *np = dev->of_node;
420
484
 	struct sc27xx_adc_data *sc27xx_data;
421
485
 	struct iio_dev *indio_dev;
422
486
 	int ret;
423
487
 
424
-	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data));
488
+	indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
425
489
 	if (!indio_dev)
426
490
 		return -ENOMEM;
427
491
 
428
492
 	sc27xx_data = iio_priv(indio_dev);
429
493
 
430
-	sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL);
494
+	sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
431
495
 	if (!sc27xx_data->regmap) {
432
-		dev_err(&pdev->dev, "failed to get ADC regmap\n");
496
+		dev_err(dev, "failed to get ADC regmap\n");
433
497
 		return -ENODEV;
434
498
 	}
435
499
 
436
500
 	ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
437
501
 	if (ret) {
438
-		dev_err(&pdev->dev, "failed to get ADC base address\n");
502
+		dev_err(dev, "failed to get ADC base address\n");
439
503
 		return ret;
440
504
 	}
441
505
 
442
506
 	sc27xx_data->irq = platform_get_irq(pdev, 0);
443
-	if (sc27xx_data->irq < 0) {
444
-		dev_err(&pdev->dev, "failed to get ADC irq number\n");
507
+	if (sc27xx_data->irq < 0)
445
508
 		return sc27xx_data->irq;
446
-	}
447
509
 
448
510
 	ret = of_hwspin_lock_get_id(np, 0);
449
511
 	if (ret < 0) {
450
-		dev_err(&pdev->dev, "failed to get hwspinlock id\n");
512
+		dev_err(dev, "failed to get hwspinlock id\n");
451
513
 		return ret;
452
514
 	}
453
515
 
454
-	sc27xx_data->hwlock = hwspin_lock_request_specific(ret);
516
+	sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
455
517
 	if (!sc27xx_data->hwlock) {
456
-		dev_err(&pdev->dev, "failed to request hwspinlock\n");
518
+		dev_err(dev, "failed to request hwspinlock\n");
457
519
 		return -ENXIO;
458
520
 	}
459
521
 
460
-	ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock,
461
-			      sc27xx_data->hwlock);
462
-	if (ret) {
463
-		sc27xx_adc_free_hwlock(sc27xx_data->hwlock);
464
-		dev_err(&pdev->dev, "failed to add hwspinlock action\n");
465
-		return ret;
466
-	}
467
-
468
-	init_completion(&sc27xx_data->completion);
469
-	sc27xx_data->dev = &pdev->dev;
522
+	sc27xx_data->dev = dev;
470
523
 
471
524
 	ret = sc27xx_adc_enable(sc27xx_data);
472
525
 	if (ret) {
473
-		dev_err(&pdev->dev, "failed to enable ADC module\n");
526
+		dev_err(dev, "failed to enable ADC module\n");
474
527
 		return ret;
475
528
 	}
476
529
 
477
-	ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data);
530
+	ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
478
531
 	if (ret) {
479
-		sc27xx_adc_disable(sc27xx_data);
480
-		dev_err(&pdev->dev, "failed to add ADC disable action\n");
532
+		dev_err(dev, "failed to add ADC disable action\n");
481
533
 		return ret;
482
534
 	}
483
535
 
484
-	ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL,
485
-					sc27xx_adc_isr, IRQF_ONESHOT,
486
-					pdev->name, sc27xx_data);
487
-	if (ret) {
488
-		dev_err(&pdev->dev, "failed to request ADC irq\n");
489
-		return ret;
490
-	}
491
-
492
-	indio_dev->dev.parent = &pdev->dev;
493
-	indio_dev->name = dev_name(&pdev->dev);
536
+	indio_dev->name = dev_name(dev);
494
537
 	indio_dev->modes = INDIO_DIRECT_MODE;
495
538
 	indio_dev->info = &sc27xx_info;
496
539
 	indio_dev->channels = sc27xx_channels;
497
540
 	indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
498
-	ret = devm_iio_device_register(&pdev->dev, indio_dev);
541
+	ret = devm_iio_device_register(dev, indio_dev);
499
542
 	if (ret)
500
-		dev_err(&pdev->dev, "could not register iio (ADC)");
543
+		dev_err(dev, "could not register iio (ADC)");
501
544
 
502
545
 	return ret;
503
546
 }