add stmac read mac form eeprom

hc

2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/v3d/v3d_debugfs.c
..
..
@@ -6,7 +6,8 @@
6
6
 #include <linux/debugfs.h>
7
7
 #include <linux/pm_runtime.h>
8
8
 #include <linux/seq_file.h>
9
-#include <drm/drmP.h>
9
+
10
+#include <drm/drm_debugfs.h>
10
11
 
11
12
 #include "v3d_drv.h"
12
13
 #include "v3d_regs.h"
..
..
@@ -26,6 +27,11 @@
26
27
 	REGDEF(V3D_HUB_IDENT3),
27
28
 	REGDEF(V3D_HUB_INT_STS),
28
29
 	REGDEF(V3D_HUB_INT_MSK_STS),
30
+
31
+	REGDEF(V3D_MMU_CTL),
32
+	REGDEF(V3D_MMU_VIO_ADDR),
33
+	REGDEF(V3D_MMU_VIO_ID),
34
+	REGDEF(V3D_MMU_DEBUG_INFO),
29
35
 };
30
36
 
31
37
 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
..
..
@@ -50,12 +56,25 @@
50
56
 	REGDEF(V3D_PTB_BPCA),
51
57
 	REGDEF(V3D_PTB_BPCS),
52
58
 
53
-	REGDEF(V3D_MMU_CTL),
54
-	REGDEF(V3D_MMU_VIO_ADDR),
55
-
56
59
 	REGDEF(V3D_GMP_STATUS),
57
60
 	REGDEF(V3D_GMP_CFG),
58
61
 	REGDEF(V3D_GMP_VIO_ADDR),
62
+
63
+	REGDEF(V3D_ERR_FDBGO),
64
+	REGDEF(V3D_ERR_FDBGB),
65
+	REGDEF(V3D_ERR_FDBGS),
66
+	REGDEF(V3D_ERR_STAT),
67
+};
68
+
69
+static const struct v3d_reg_def v3d_csd_reg_defs[] = {
70
+	REGDEF(V3D_CSD_STATUS),
71
+	REGDEF(V3D_CSD_CURRENT_CFG0),
72
+	REGDEF(V3D_CSD_CURRENT_CFG1),
73
+	REGDEF(V3D_CSD_CURRENT_CFG2),
74
+	REGDEF(V3D_CSD_CURRENT_CFG3),
75
+	REGDEF(V3D_CSD_CURRENT_CFG4),
76
+	REGDEF(V3D_CSD_CURRENT_CFG5),
77
+	REGDEF(V3D_CSD_CURRENT_CFG6),
59
78
 };
60
79
 
61
80
 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
..
..
@@ -89,6 +108,17 @@
89
108
 				   V3D_CORE_READ(core,
90
109
 						 v3d_core_reg_defs[i].reg));
91
110
 		}
111
+
112
+		if (v3d_has_csd(v3d)) {
113
+			for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
114
+				seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
115
+					   core,
116
+					   v3d_csd_reg_defs[i].name,
117
+					   v3d_csd_reg_defs[i].reg,
118
+					   V3D_CORE_READ(core,
119
+							 v3d_csd_reg_defs[i].reg));
120
+			}
121
+		}
92
122
 	}
93
123
 
94
124
 	return 0;
..
..
@@ -102,7 +132,7 @@
102
132
 	u32 ident0, ident1, ident2, ident3, cores;
103
133
 	int ret, core;
104
134
 
105
-	ret = pm_runtime_get_sync(v3d->dev);
135
+	ret = pm_runtime_get_sync(v3d->drm.dev);
106
136
 	if (ret < 0)
107
137
 		return ret;
108
138
 
..
..
@@ -157,8 +187,8 @@
157
187
 			   (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
158
188
 	}
159
189
 
160
-	pm_runtime_mark_last_busy(v3d->dev);
161
-	pm_runtime_put_autosuspend(v3d->dev);
190
+	pm_runtime_mark_last_busy(v3d->drm.dev);
191
+	pm_runtime_put_autosuspend(v3d->drm.dev);
162
192
 
163
193
 	return 0;
164
194
 }
..
..
@@ -179,16 +209,59 @@
179
209
 	return 0;
180
210
 }
181
211
 
212
+static int v3d_measure_clock(struct seq_file *m, void *unused)
213
+{
214
+	struct drm_info_node *node = (struct drm_info_node *)m->private;
215
+	struct drm_device *dev = node->minor->dev;
216
+	struct v3d_dev *v3d = to_v3d_dev(dev);
217
+	uint32_t cycles;
218
+	int core = 0;
219
+	int measure_ms = 1000;
220
+	int ret;
221
+
222
+	ret = pm_runtime_get_sync(v3d->drm.dev);
223
+	if (ret < 0)
224
+		return ret;
225
+
226
+	if (v3d->ver >= 40) {
227
+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
228
+			       V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
229
+					     V3D_PCTR_S0));
230
+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
231
+		V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
232
+	} else {
233
+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
234
+			       V3D_PCTR_CYCLE_COUNT);
235
+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
236
+		V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
237
+			       V3D_V3_PCTR_0_EN_ENABLE |
238
+			       1);
239
+	}
240
+	msleep(measure_ms);
241
+	cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
242
+
243
+	seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
244
+		   cycles,
245
+		   cycles / (measure_ms * 1000),
246
+		   (cycles / (measure_ms * 100)) % 10);
247
+
248
+	pm_runtime_mark_last_busy(v3d->drm.dev);
249
+	pm_runtime_put_autosuspend(v3d->drm.dev);
250
+
251
+	return 0;
252
+}
253
+
182
254
 static const struct drm_info_list v3d_debugfs_list[] = {
183
255
 	{"v3d_ident", v3d_v3d_debugfs_ident, 0},
184
256
 	{"v3d_regs", v3d_v3d_debugfs_regs, 0},
257
+	{"measure_clock", v3d_measure_clock, 0},
185
258
 	{"bo_stats", v3d_debugfs_bo_stats, 0},
186
259
 };
187
260
 
188
-int
261
+void
189
262
 v3d_debugfs_init(struct drm_minor *minor)
190
263
 {
191
-	return drm_debugfs_create_files(v3d_debugfs_list,
192
-					ARRAY_SIZE(v3d_debugfs_list),
193
-					minor->debugfs_root, minor);
264
+	drm_debugfs_create_files(v3d_debugfs_list,
265
+				 ARRAY_SIZE(v3d_debugfs_list),
266
+				 minor->debugfs_root, minor);
194
267
 }