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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h
....@@ -1,23 +1,13 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34  * Author: Chris Zhong <zyw@rock-chips.com>
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 
157 #ifndef _CDN_DP_REG_H
168 #define _CDN_DP_REG_H
179 
1810 #include <linux/bitops.h>
19
-#include <linux/phy/phy.h>
20
-#include <linux/phy/phy-rockchip-typec.h>
2111 
2212 #define ADDR_IMEM		0x10000
2313 #define ADDR_DMEM		0x20000
....@@ -139,7 +129,7 @@
139129 #define HPD_EVENT_MASK			0x211c
140130 #define HPD_EVENT_DET			0x2120
141131 
142
-/* dptx framer addr */
132
+/* dpyx framer addr */
143133 #define DP_FRAMER_GLOBAL_CONFIG		0x2200
144134 #define DP_SW_RESET			0x2204
145135 #define DP_FRAMER_TU			0x2208
....@@ -330,13 +320,6 @@
330320 #define GENERAL_BUS_SETTINGS            0x03
331321 #define GENERAL_TEST_ACCESS             0x04
332322 
333
-/* AUX status*/
334
-#define AUX_STATUS_ACK			0
335
-#define AUX_STATUS_NACK			1
336
-#define AUX_STATUS_DEFER			2
337
-#define AUX_STATUS_SINK_ERROR		3
338
-#define AUX_STATUS_BUS_ERROR		4
339
-
340323 #define DPTX_SET_POWER_MNG			0x00
341324 #define DPTX_SET_HOST_CAPABILITIES		0x01
342325 #define DPTX_GET_EDID				0x02
....@@ -430,54 +413,8 @@
430413 #define SPDIF_JITTER_THRSH(x)			(((x) & 0xff) << 3)
431414 #define SPDIF_JITTER_AVG_WIN(x)			((x) & 0x7)
432415 
433
-/* SOURCE_PIF_WR_REQ */
434
-#define HOST_WR			BIT(0)
435
-
436
-/* SOURCE_PIF_PKT_ALLOC_REG */
437
-#define ACTIVE_IDLE_TYPE(x)	(((x) & 0x1) << 17)
438
-#define TYPE_VALID		BIT(16)
439
-#define PACKET_TYPE(x)		(((x) & 0xff) << 8)
440
-#define PKT_ALLOC_ADDRESS(x)	(((x) & 0xf) << 0)
441
-
442
-/* SOURCE_PIF_PKT_ALLOC_WR_EN */
443
-#define PKT_ALLOC_WR_EN		BIT(0)
444
-
445416 /* Reference cycles when using lane clock as reference */
446417 #define LANE_REF_CYC				0x8000
447
-
448
-/* register CM_VID_CTRL */
449
-#define LANE_VID_REF_CYC(x)                    (((x) & (BIT(24) - 1)) << 0)
450
-#define NMVID_MEAS_TOLERANCE(x)                        (((x) & 0xf) << 24)
451
-
452
-/* register DP_TX_PHY_CONFIG_REG */
453
-#define DP_TX_PHY_TRAINING_ENABLE(x)           ((x) & 1)
454
-#define DP_TX_PHY_TRAINING_TYPE_PRBS7          (0 << 1)
455
-#define DP_TX_PHY_TRAINING_TYPE_TPS1           (1 << 1)
456
-#define DP_TX_PHY_TRAINING_TYPE_TPS2           (2 << 1)
457
-#define DP_TX_PHY_TRAINING_TYPE_TPS3           (3 << 1)
458
-#define DP_TX_PHY_TRAINING_TYPE_TPS4           (4 << 1)
459
-#define DP_TX_PHY_TRAINING_TYPE_PLTPAT         (5 << 1)
460
-#define DP_TX_PHY_TRAINING_TYPE_D10_2          (6 << 1)
461
-#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT       (8 << 1)
462
-#define DP_TX_PHY_TRAINING_PATTERN(x)          ((x) << 1)
463
-#define DP_TX_PHY_SCRAMBLER_BYPASS(x)          (((x) & 1) << 5)
464
-#define DP_TX_PHY_ENCODER_BYPASS(x)            (((x) & 1) << 6)
465
-#define DP_TX_PHY_SKEW_BYPASS(x)               (((x) & 1) << 7)
466
-#define DP_TX_PHY_DISPARITY_RST(x)             (((x) & 1) << 8)
467
-#define DP_TX_PHY_LANE0_SKEW(x)                (((x) & 7) << 9)
468
-#define DP_TX_PHY_LANE1_SKEW(x)                (((x) & 7) << 12)
469
-#define DP_TX_PHY_LANE2_SKEW(x)                (((x) & 7) << 15)
470
-#define DP_TX_PHY_LANE3_SKEW(x)                (((x) & 7) << 18)
471
-#define DP_TX_PHY_10BIT_ENABLE(x)              (((x) & 1) << 21)
472
-
473
-/* register DP_FRAMER_GLOBAL_CONFIG */
474
-#define NUM_LANES(x)           ((x) & 3)
475
-#define SST_MODE               (0 << 2)
476
-#define RG_EN                  (0 << 4)
477
-#define GLOBAL_EN              BIT(3)
478
-#define NO_VIDEO               BIT(5)
479
-#define ENC_RST_DIS            BIT(6)
480
-#define WR_VHSYNC_FALL         BIT(7)
481418 
482419 enum voltage_swing_level {
483420 	VOLTAGE_LEVEL_0,
....@@ -524,12 +461,8 @@
524461 int cdn_dp_event_config(struct cdn_dp_device *dp);
525462 u32 cdn_dp_get_event(struct cdn_dp_device *dp);
526463 int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
527
-int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
528
-ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
529
-			  u8 *data, u16 len);
530
-ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
531
-			 u8 *data, u16 len);
532
-int cdn_dp_get_aux_status(struct cdn_dp_device *dp);
464
+int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
465
+int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
533466 int cdn_dp_get_edid_block(void *dp, u8 *edid,
534467 			  unsigned int block, size_t length);
535468 int cdn_dp_train_link(struct cdn_dp_device *dp);
....@@ -538,7 +471,4 @@
538471 int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
539472 int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
540473 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
541
-int cdn_dp_software_train_link(struct cdn_dp_device *dp);
542
-void cdn_dp_infoframe_set(struct cdn_dp_device *dp, int entry_id, u8 *buf,
543
-			  u32 len, int type);
544474 #endif /* _CDN_DP_REG_H */