add stmac read mac form eeprom

hc

2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/radeon/radeon_legacy_tv.c
..
..
@@ -1,6 +1,8 @@
1
-// SPDX-License-Identifier: GPL-2.0
2
-#include <drm/drmP.h>
1
+// SPDX-License-Identifier: MIT
2
+
3
3
 #include <drm/drm_crtc_helper.h>
4
+#include <drm/drm_device.h>
5
+
4
6
 #include "radeon.h"
5
7
 
6
8
 /*
..
..
@@ -421,24 +423,14 @@
421
423
 
422
424
 static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder)
423
425
 {
424
-	struct drm_device *dev = encoder->dev;
425
-	struct radeon_device *rdev = dev->dev_private;
426
426
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
427
427
 	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
428
-	struct radeon_crtc *radeon_crtc;
429
428
 	int restart;
430
429
 	unsigned int h_total, v_total, f_total;
431
430
 	int v_offset, h_offset;
432
431
 	u16 p1, p2, h_inc;
433
432
 	bool h_changed;
434
433
 	const struct radeon_tv_mode_constants *const_ptr;
435
-	struct radeon_pll *pll;
436
-
437
-	radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);
438
-	if (radeon_crtc->crtc_id == 1)
439
-		pll = &rdev->clock.p2pll;
440
-	else
441
-		pll = &rdev->clock.p1pll;
442
434
 
443
435
 	const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL);
444
436
 	if (!const_ptr)
..
..
@@ -545,7 +537,7 @@
545
537
 	uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
546
538
 	uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
547
539
 	uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
548
-	uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
540
+	uint32_t tv_pll_cntl, tv_ftotal;
549
541
 	uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
550
542
 	uint32_t m, n, p;
551
543
 	const uint16_t *hor_timing;
..
..
@@ -716,12 +708,6 @@
716
708
 		((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
717
709
 		(((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
718
710
 		((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
719
-
720
-	tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) |
721
-			((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
722
-			((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) |
723
-			RADEON_TVCLK_SRC_SEL_TVPLL |
724
-			RADEON_TVPLL_TEST_DIS);
725
711
 
726
712
 	tv_dac->tv.tv_uv_adr = 0xc8;
727
713