forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/gpu/drm/radeon/r100.c
....@@ -25,24 +25,30 @@
2525  *          Alex Deucher
2626  *          Jerome Glisse
2727  */
28
-#include <linux/seq_file.h>
29
-#include <linux/slab.h>
30
-#include <drm/drmP.h>
31
-#include <drm/radeon_drm.h>
32
-#include "radeon_reg.h"
33
-#include "radeon.h"
34
-#include "radeon_asic.h"
35
-#include "r100d.h"
36
-#include "rs100d.h"
37
-#include "rv200d.h"
38
-#include "rv250d.h"
39
-#include "atom.h"
4028 
4129 #include <linux/firmware.h>
4230 #include <linux/module.h>
31
+#include <linux/pci.h>
32
+#include <linux/seq_file.h>
33
+#include <linux/slab.h>
4334 
35
+#include <drm/drm_debugfs.h>
36
+#include <drm/drm_device.h>
37
+#include <drm/drm_file.h>
38
+#include <drm/drm_fourcc.h>
39
+#include <drm/drm_vblank.h>
40
+#include <drm/radeon_drm.h>
41
+
42
+#include "atom.h"
4443 #include "r100_reg_safe.h"
44
+#include "r100d.h"
45
+#include "radeon.h"
46
+#include "radeon_asic.h"
47
+#include "radeon_reg.h"
4548 #include "rn50_reg_safe.h"
49
+#include "rs100d.h"
50
+#include "rv200d.h"
51
+#include "rv250d.h"
4652 
4753 /* Firmware Names */
4854 #define FIRMWARE_R100		"radeon/R100_cp.bin"
....@@ -885,7 +891,7 @@
885891 				    uint64_t src_offset,
886892 				    uint64_t dst_offset,
887893 				    unsigned num_gpu_pages,
888
-				    struct reservation_object *resv)
894
+				    struct dma_resv *resv)
889895 {
890896 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
891897 	struct radeon_fence *fence;
....@@ -1817,9 +1823,9 @@
18171823 	case RADEON_PP_TXFORMAT_2:
18181824 		i = (reg - RADEON_PP_TXFORMAT_0) / 24;
18191825 		if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1820
-			track->textures[i].use_pitch = 1;
1826
+			track->textures[i].use_pitch = true;
18211827 		} else {
1822
-			track->textures[i].use_pitch = 0;
1828
+			track->textures[i].use_pitch = false;
18231829 			track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
18241830 			track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
18251831 		}
....@@ -2381,12 +2387,12 @@
23812387 		else
23822388 			track->num_texture = 6;
23832389 		track->maxy = 2048;
2384
-		track->separate_cube = 1;
2390
+		track->separate_cube = true;
23852391 	} else {
23862392 		track->num_cb = 4;
23872393 		track->num_texture = 16;
23882394 		track->maxy = 4096;
2389
-		track->separate_cube = 0;
2395
+		track->separate_cube = false;
23902396 		track->aaresolve = false;
23912397 		track->aa.robj = NULL;
23922398 	}
....@@ -2470,7 +2476,7 @@
24702476 		if (tmp >= n) {
24712477 			return 0;
24722478 		}
2473
-		DRM_UDELAY(1);
2479
+		udelay(1);
24742480 	}
24752481 	return -1;
24762482 }
....@@ -2488,7 +2494,7 @@
24882494 		if (!(tmp & RADEON_RBBM_ACTIVE)) {
24892495 			return 0;
24902496 		}
2491
-		DRM_UDELAY(1);
2497
+		udelay(1);
24922498 	}
24932499 	return -1;
24942500 }
....@@ -2504,7 +2510,7 @@
25042510 		if (tmp & RADEON_MC_IDLE) {
25052511 			return 0;
25062512 		}
2507
-		DRM_UDELAY(1);
2513
+		udelay(1);
25082514 	}
25092515 	return -1;
25102516 }
....@@ -2809,7 +2815,7 @@
28092815 	uint32_t temp;
28102816 
28112817 	temp = RREG32(RADEON_CONFIG_CNTL);
2812
-	if (state == false) {
2818
+	if (!state) {
28132819 		temp &= ~RADEON_CFG_VGA_RAM_EN;
28142820 		temp |= RADEON_CFG_VGA_IO_DIS;
28152821 	} else {
....@@ -3669,7 +3675,7 @@
36693675 		if (tmp == 0xDEADBEEF) {
36703676 			break;
36713677 		}
3672
-		DRM_UDELAY(1);
3678
+		udelay(1);
36733679 	}
36743680 	if (i < rdev->usec_timeout) {
36753681 		DRM_INFO("ring test succeeded in %d usecs\n", i);
....@@ -3746,7 +3752,7 @@
37463752 		if (tmp == 0xDEADBEEF) {
37473753 			break;
37483754 		}
3749
-		DRM_UDELAY(1);
3755
+		udelay(1);
37503756 	}
37513757 	if (i < rdev->usec_timeout) {
37523758 		DRM_INFO("ib test succeeded in %u usecs\n", i);