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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/radeon/cik.c
..
..
@@ -21,18 +21,22 @@
21
21
  *
22
22
  * Authors: Alex Deucher
23
23
  */
24
+
24
25
 #include <linux/firmware.h>
25
-#include <linux/slab.h>
26
26
 #include <linux/module.h>
27
-#include <drm/drmP.h>
27
+#include <linux/pci.h>
28
+#include <linux/slab.h>
29
+
30
+#include <drm/drm_vblank.h>
31
+
32
+#include "atom.h"
33
+#include "cik_blit_shaders.h"
34
+#include "cikd.h"
35
+#include "clearstate_ci.h"
28
36
 #include "radeon.h"
29
37
 #include "radeon_asic.h"
30
38
 #include "radeon_audio.h"
31
-#include "cikd.h"
32
-#include "atom.h"
33
-#include "cik_blit_shaders.h"
34
39
 #include "radeon_ucode.h"
35
-#include "clearstate_ci.h"
36
40
 
37
41
 #define SH_MEM_CONFIG_GFX_DEFAULT \
38
42
 	ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
..
..
@@ -217,9 +221,7 @@
217
221
 	else
218
222
 		actual_temp = temp & 0x1ff;
219
223
 
220
-	actual_temp = actual_temp * 1000;
221
-
222
-	return actual_temp;
224
+	return actual_temp * 1000;
223
225
 }
224
226
 
225
227
 /* get temperature in millidegrees */
..
..
@@ -235,9 +237,7 @@
235
237
 	else
236
238
 		actual_temp = 0;
237
239
 
238
-	actual_temp = actual_temp * 1000;
239
-
240
-	return actual_temp;
240
+	return actual_temp * 1000;
241
241
 }
242
242
 
243
243
 /*
..
..
@@ -3480,7 +3480,7 @@
3480
3480
 		tmp = RREG32(scratch);
3481
3481
 		if (tmp == 0xDEADBEEF)
3482
3482
 			break;
3483
-		DRM_UDELAY(1);
3483
+		udelay(1);
3484
3484
 	}
3485
3485
 	if (i < rdev->usec_timeout) {
3486
3486
 		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
..
..
@@ -3655,7 +3655,7 @@
3655
3655
 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
3656
3656
 				    uint64_t src_offset, uint64_t dst_offset,
3657
3657
 				    unsigned num_gpu_pages,
3658
-				    struct reservation_object *resv)
3658
+				    struct dma_resv *resv)
3659
3659
 {
3660
3660
 	struct radeon_fence *fence;
3661
3661
 	struct radeon_sync sync;
..
..
@@ -3825,7 +3825,7 @@
3825
3825
 		tmp = RREG32(scratch);
3826
3826
 		if (tmp == 0xDEADBEEF)
3827
3827
 			break;
3828
-		DRM_UDELAY(1);
3828
+		udelay(1);
3829
3829
 	}
3830
3830
 	if (i < rdev->usec_timeout) {
3831
3831
 		DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
..
..
@@ -8137,7 +8137,7 @@
8137
8137
 		 * there. So it is pointless to try to go through that code
8138
8138
 		 * hence why we disable uvd here.
8139
8139
 		 */
8140
-		rdev->has_uvd = 0;
8140
+		rdev->has_uvd = false;
8141
8141
 		return;
8142
8142
 	}
8143
8143
 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
..
..
@@ -8209,7 +8209,7 @@
8209
8209
 		 * there. So it is pointless to try to go through that code
8210
8210
 		 * hence why we disable vce here.
8211
8211
 		 */
8212
-		rdev->has_vce = 0;
8212
+		rdev->has_vce = false;
8213
8213
 		return;
8214
8214
 	}
8215
8215
 	rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
..
..
@@ -9500,7 +9500,6 @@
9500
9500
 {
9501
9501
 	struct pci_dev *root = rdev->pdev->bus->self;
9502
9502
 	enum pci_bus_speed speed_cap;
9503
-	int bridge_pos, gpu_pos;
9504
9503
 	u32 speed_cntl, current_data_rate;
9505
9504
 	int i;
9506
9505
 	u16 tmp16;
..
..
@@ -9542,12 +9541,7 @@
9542
9541
 		DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
9543
9542
 	}
9544
9543
 
9545
-	bridge_pos = pci_pcie_cap(root);
9546
-	if (!bridge_pos)
9547
-		return;
9548
-
9549
-	gpu_pos = pci_pcie_cap(rdev->pdev);
9550
-	if (!gpu_pos)
9544
+	if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))
9551
9545
 		return;
9552
9546
 
9553
9547
 	if (speed_cap == PCIE_SPEED_8_0GT) {
..
..
@@ -9557,14 +9551,17 @@
9557
9551
 			u16 bridge_cfg2, gpu_cfg2;
9558
9552
 			u32 max_lw, current_lw, tmp;
9559
9553
 
9560
-			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9561
-			pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9554
+			pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9555
+						  &bridge_cfg);
9556
+			pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
9557
+						  &gpu_cfg);
9562
9558
 
9563
9559
 			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
9564
-			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9560
+			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
9565
9561
 
9566
9562
 			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
9567
-			pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9563
+			pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
9564
+						   tmp16);
9568
9565
 
9569
9566
 			tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9570
9567
 			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
..
..
@@ -9582,15 +9579,23 @@
9582
9579
 
9583
9580
 			for (i = 0; i < 10; i++) {
9584
9581
 				/* check status */
9585
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
9582
+				pcie_capability_read_word(rdev->pdev,
9583
+							  PCI_EXP_DEVSTA,
9584
+							  &tmp16);
9586
9585
 				if (tmp16 & PCI_EXP_DEVSTA_TRPND)
9587
9586
 					break;
9588
9587
 
9589
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9590
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9588
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9589
+							  &bridge_cfg);
9590
+				pcie_capability_read_word(rdev->pdev,
9591
+							  PCI_EXP_LNKCTL,
9592
+							  &gpu_cfg);
9591
9593
 
9592
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
9593
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
9594
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9595
+							  &bridge_cfg2);
9596
+				pcie_capability_read_word(rdev->pdev,
9597
+							  PCI_EXP_LNKCTL2,
9598
+							  &gpu_cfg2);
9594
9599
 
9595
9600
 				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9596
9601
 				tmp |= LC_SET_QUIESCE;
..
..
@@ -9600,29 +9605,48 @@
9600
9605
 				tmp |= LC_REDO_EQ;
9601
9606
 				WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9602
9607
 
9603
-				mdelay(100);
9608
+				msleep(100);
9604
9609
 
9605
9610
 				/* linkctl */
9606
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
9611
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL,
9612
+							  &tmp16);
9607
9613
 				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9608
9614
 				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
9609
-				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9615
+				pcie_capability_write_word(root, PCI_EXP_LNKCTL,
9616
+							   tmp16);
9610
9617
 
9611
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
9618
+				pcie_capability_read_word(rdev->pdev,
9619
+							  PCI_EXP_LNKCTL,
9620
+							  &tmp16);
9612
9621
 				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9613
9622
 				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
9614
-				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9623
+				pcie_capability_write_word(rdev->pdev,
9624
+							   PCI_EXP_LNKCTL,
9625
+							   tmp16);
9615
9626
 
9616
9627
 				/* linkctl2 */
9617
-				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
9618
-				tmp16 &= ~((1 << 4) | (7 << 9));
9619
-				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
9620
-				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
9628
+				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
9629
+							  &tmp16);
9630
+				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
9631
+					   PCI_EXP_LNKCTL2_TX_MARGIN);
9632
+				tmp16 |= (bridge_cfg2 &
9633
+					  (PCI_EXP_LNKCTL2_ENTER_COMP |
9634
+					   PCI_EXP_LNKCTL2_TX_MARGIN));
9635
+				pcie_capability_write_word(root,
9636
+							   PCI_EXP_LNKCTL2,
9637
+							   tmp16);
9621
9638
 
9622
-				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9623
-				tmp16 &= ~((1 << 4) | (7 << 9));
9624
-				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
9625
-				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9639
+				pcie_capability_read_word(rdev->pdev,
9640
+							  PCI_EXP_LNKCTL2,
9641
+							  &tmp16);
9642
+				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
9643
+					   PCI_EXP_LNKCTL2_TX_MARGIN);
9644
+				tmp16 |= (gpu_cfg2 &
9645
+					  (PCI_EXP_LNKCTL2_ENTER_COMP |
9646
+					   PCI_EXP_LNKCTL2_TX_MARGIN));
9647
+				pcie_capability_write_word(rdev->pdev,
9648
+							   PCI_EXP_LNKCTL2,
9649
+							   tmp16);
9626
9650
 
9627
9651
 				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9628
9652
 				tmp &= ~LC_SET_QUIESCE;
..
..
@@ -9636,15 +9660,15 @@
9636
9660
 	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
9637
9661
 	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9638
9662
 
9639
-	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9640
-	tmp16 &= ~0xf;
9663
+	pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);
9664
+	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
9641
9665
 	if (speed_cap == PCIE_SPEED_8_0GT)
9642
-		tmp16 |= 3; /* gen3 */
9666
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
9643
9667
 	else if (speed_cap == PCIE_SPEED_5_0GT)
9644
-		tmp16 |= 2; /* gen2 */
9668
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
9645
9669
 	else
9646
-		tmp16 |= 1; /* gen1 */
9647
-	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9670
+		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
9671
+	pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);
9648
9672
 
9649
9673
 	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9650
9674
 	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;