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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/msm/msm_gpu.h
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@@ -1,29 +1,22 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2013 Red Hat
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  * Author: Rob Clark <robdclark@gmail.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published by
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- * the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License along with
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- * this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __MSM_GPU_H__
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 #define __MSM_GPU_H__
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9
 
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+#include <linux/adreno-smmu-priv.h>
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 #include <linux/clk.h>
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+#include <linux/interconnect.h>
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+#include <linux/pm_opp.h>
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 #include <linux/regulator/consumer.h>
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 #include "msm_drv.h"
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 #include "msm_fence.h"
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 #include "msm_ringbuffer.h"
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+#include "msm_gem.h"
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 struct msm_gem_submit;
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 struct msm_gpu_perfcntr;
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@@ -31,9 +24,6 @@
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 struct msm_gpu_config {
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 	const char *ioname;
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-	const char *irqname;
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-	uint64_t va_start;
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-	uint64_t va_end;
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 	unsigned int nr_rings;
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 };
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@@ -56,8 +46,7 @@
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 	int (*hw_init)(struct msm_gpu *gpu);
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 	int (*pm_suspend)(struct msm_gpu *gpu);
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 	int (*pm_resume)(struct msm_gpu *gpu);
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-	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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-			struct msm_file_private *ctx);
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+	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
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 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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 	irqreturn_t (*irq)(struct msm_gpu *irq);
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 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
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@@ -68,11 +57,18 @@
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 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
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 			struct drm_printer *p);
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 	/* for generation specific debugfs: */
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-	int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
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+	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
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 #endif
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-	int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
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+	unsigned long (*gpu_busy)(struct msm_gpu *gpu);
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 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
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 	int (*gpu_state_put)(struct msm_gpu_state *state);
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+	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
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+	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp);
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+	struct msm_gem_address_space *(*create_address_space)
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+		(struct msm_gpu *gpu, struct platform_device *pdev);
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+	struct msm_gem_address_space *(*create_private_address_space)
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+		(struct msm_gpu *gpu);
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+	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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 };
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 struct msm_gpu {
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@@ -80,6 +76,8 @@
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 	struct drm_device *dev;
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 	struct platform_device *pdev;
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 	const struct msm_gpu_funcs *funcs;
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+
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+	struct adreno_smmu_priv adreno_smmu;
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 	/* performance counters (hw & sw): */
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 	spinlock_t perf_lock;
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@@ -102,6 +100,9 @@
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 	/* does gpu need hw_init? */
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 	bool needs_hw_init;
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+	/* number of GPU hangs (for all contexts) */
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+	int global_faults;
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+
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 	/* worker for handling active-list retiring: */
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 	struct work_struct retire_work;
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@@ -116,6 +117,15 @@
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 	int nr_clocks;
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 	struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk;
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 	uint32_t fast_rate;
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+
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+	/* The gfx-mem interconnect path that's used by all GPU types. */
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+	struct icc_path *icc_path;
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+
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+	/*
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+	 * Second interconnect path for some A3xx and all A4xx GPUs to the
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+	 * On Chip MEMory (OCMEM).
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+	 */
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+	struct icc_path *ocmem_icc_path;
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 	/* Hang and Inactivity Detection:
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 	 */
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@@ -135,7 +145,15 @@
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 	} devfreq;
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 	struct msm_gpu_state *crashstate;
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+	/* True if the hardware supports expanded apriv (a650 and newer) */
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+	bool hw_apriv;
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 };
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+
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+static inline struct msm_gpu *dev_to_gpu(struct device *dev)
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+{
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+	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev);
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+	return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);
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+}
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 /* It turns out that all targets use the same ringbuffer size */
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 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
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@@ -177,6 +195,7 @@
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 	u32 flags;
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 	u32 prio;
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 	int faults;
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+	struct msm_file_private *ctx;
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 	struct list_head node;
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 	struct kref ref;
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 };
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@@ -185,6 +204,7 @@
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 	u64 iova;
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 	size_t size;
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 	void *data;
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+	bool encoded;
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 };
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 struct msm_gpu_state {
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@@ -199,6 +219,7 @@
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 		u32 wptr;
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 		void *data;
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 		int data_size;
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+		bool encoded;
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 	} ring[MSM_GPU_MAX_RINGS];
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 	int nr_registers;
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@@ -264,6 +285,7 @@
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 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
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 int msm_gpu_pm_resume(struct msm_gpu *gpu);
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+void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
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 int msm_gpu_hw_init(struct msm_gpu *gpu);
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@@ -273,12 +295,14 @@
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 		uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs);
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 void msm_gpu_retire(struct msm_gpu *gpu);
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-void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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-		struct msm_file_private *ctx);
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+void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
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 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
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 		const char *name, struct msm_gpu_config *config);
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+
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+struct msm_gem_address_space *
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+msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
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 void msm_gpu_cleanup(struct msm_gpu *gpu);
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@@ -320,4 +344,12 @@
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 	mutex_unlock(&gpu->dev->struct_mutex);
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 }
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+/*
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+ * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
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+ * support expanded privileges
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+ */
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+#define check_apriv(gpu, flags) \
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+	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
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+
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+
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 #endif /* __MSM_GPU_H__ */