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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/msm/adreno/a5xx_preempt.c
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@@ -1,14 +1,5 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /* Copyright (c) 2017 The Linux Foundation. All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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3
  */
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4
 
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 #include "msm_gem.h"
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@@ -92,7 +83,7 @@
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 	if (!try_preempt_state(a5xx_gpu, PREEMPT_TRIGGERED, PREEMPT_FAULTED))
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 		return;
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-	dev_err(dev->dev, "%s: preemption timed out\n", gpu->name);
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+	DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name);
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 	queue_work(priv->wq, &gpu->recover_work);
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 }
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@@ -188,7 +179,7 @@
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 	status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL);
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 	if (unlikely(status)) {
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 		set_preempt_state(a5xx_gpu, PREEMPT_FAULTED);
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-		dev_err(dev->dev, "%s: Preemption failed to complete\n",
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+		DRM_DEV_ERROR(dev->dev, "%s: Preemption failed to complete\n",
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 			gpu->name);
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 		queue_work(priv->wq, &gpu->recover_work);
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 		return;
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@@ -208,6 +199,13 @@
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 	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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 	int i;
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+	/* Always come up on rb 0 */
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+	a5xx_gpu->cur_ring = gpu->rb[0];
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+
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+	/* No preemption if we only have one ring */
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+	if (gpu->nr_rings == 1)
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+		return;
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+
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 	for (i = 0; i < gpu->nr_rings; i++) {
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 		a5xx_gpu->preempt[i]->wptr = 0;
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 		a5xx_gpu->preempt[i]->rptr = 0;
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@@ -220,9 +218,6 @@
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 	/* Reset the preemption state */
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 	set_preempt_state(a5xx_gpu, PREEMPT_NONE);
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-
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-	/* Always come up on rb 0 */
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-	a5xx_gpu->cur_ring = gpu->rb[0];
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 }
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 static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu,
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@@ -231,17 +226,31 @@
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 	struct adreno_gpu *adreno_gpu = &a5xx_gpu->base;
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 	struct msm_gpu *gpu = &adreno_gpu->base;
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 	struct a5xx_preempt_record *ptr;
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-	struct drm_gem_object *bo = NULL;
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-	u64 iova = 0;
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+	void *counters;
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+	struct drm_gem_object *bo = NULL, *counters_bo = NULL;
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+	u64 iova = 0, counters_iova = 0;
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232
 
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 	ptr = msm_gem_kernel_new(gpu->dev,
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 		A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE,
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-		MSM_BO_UNCACHED, gpu->aspace, &bo, &iova);
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+		MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova);
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236
 
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 	if (IS_ERR(ptr))
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 		return PTR_ERR(ptr);
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+	/* The buffer to store counters needs to be unprivileged */
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+	counters = msm_gem_kernel_new(gpu->dev,
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+		A5XX_PREEMPT_COUNTER_SIZE,
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+		MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova);
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+	if (IS_ERR(counters)) {
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+		msm_gem_kernel_put(bo, gpu->aspace, true);
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+		return PTR_ERR(counters);
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+	}
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+
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+	msm_gem_object_set_name(bo, "preempt");
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+	msm_gem_object_set_name(counters_bo, "preempt_counters");
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+
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 	a5xx_gpu->preempt_bo[ring->id] = bo;
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+	a5xx_gpu->preempt_counters_bo[ring->id] = counters_bo;
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 	a5xx_gpu->preempt_iova[ring->id] = iova;
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 	a5xx_gpu->preempt[ring->id] = ptr;
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@@ -250,9 +259,10 @@
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 	ptr->magic = A5XX_PREEMPT_RECORD_MAGIC;
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 	ptr->info = 0;
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 	ptr->data = 0;
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-	ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT;
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-	ptr->rptr_addr = rbmemptr(ring, rptr);
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-	ptr->counter = iova + A5XX_PREEMPT_RECORD_SIZE;
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+	ptr->cntl = MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE;
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+
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+	ptr->rptr_addr = shadowptr(a5xx_gpu, ring);
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+	ptr->counter = counters_iova;
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 	return 0;
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 }
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@@ -264,16 +274,9 @@
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 	int i;
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 	for (i = 0; i < gpu->nr_rings; i++) {
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-		if (!a5xx_gpu->preempt_bo[i])
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-			continue;
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-
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-		msm_gem_put_vaddr(a5xx_gpu->preempt_bo[i]);
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-
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-		if (a5xx_gpu->preempt_iova[i])
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-			msm_gem_put_iova(a5xx_gpu->preempt_bo[i], gpu->aspace);
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-
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-		drm_gem_object_unreference(a5xx_gpu->preempt_bo[i]);
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-		a5xx_gpu->preempt_bo[i] = NULL;
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+		msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace, true);
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+		msm_gem_kernel_put(a5xx_gpu->preempt_counters_bo[i],
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+			gpu->aspace, true);
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 	}
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 }
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