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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/gpu/drm/meson/meson_venc_cvbs.c
....@@ -1,43 +1,32 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2016 BayLibre, SAS
34  * Author: Neil Armstrong <narmstrong@baylibre.com>
45  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
56  * Copyright (C) 2014 Endless Mobile
67  *
7
- * This program is free software; you can redistribute it and/or
8
- * modify it under the terms of the GNU General Public License as
9
- * published by the Free Software Foundation; either version 2 of the
10
- * License, or (at your option) any later version.
11
- *
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- * This program is distributed in the hope that it will be useful, but
13
- * WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
19
- *
208  * Written by:
219  *     Jasper St. Pierre <jstpierre@mecheye.net>
2210  */
2311 
24
-#include <linux/kernel.h>
25
-#include <linux/module.h>
12
+#include <linux/export.h>
2613 #include <linux/of_graph.h>
2714 
28
-#include <drm/drmP.h>
29
-#include <drm/drm_edid.h>
30
-#include <drm/drm_crtc_helper.h>
3115 #include <drm/drm_atomic_helper.h>
16
+#include <drm/drm_device.h>
17
+#include <drm/drm_edid.h>
18
+#include <drm/drm_probe_helper.h>
19
+#include <drm/drm_print.h>
3220 
33
-#include "meson_venc_cvbs.h"
34
-#include "meson_venc.h"
35
-#include "meson_vclk.h"
3621 #include "meson_registers.h"
22
+#include "meson_vclk.h"
23
+#include "meson_venc_cvbs.h"
3724 
3825 /* HHI VDAC Registers */
3926 #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
27
+#define HHI_VDAC_CNTL0_G12A	0x2EC /* 0xbd offset in data sheet */
4028 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
29
+#define HHI_VDAC_CNTL1_G12A	0x2F0 /* 0xbe offset in data sheet */
4130 
4231 struct meson_venc_cvbs {
4332 	struct drm_encoder	encoder;
....@@ -59,7 +48,6 @@
5948 			DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
6049 				 720, 732, 795, 864, 0, 576, 580, 586, 625, 0,
6150 				 DRM_MODE_FLAG_INTERLACE),
62
-			.vrefresh = 50,
6351 			.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
6452 		},
6553 	},
....@@ -69,7 +57,6 @@
6957 			DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
7058 				720, 739, 801, 858, 0, 480, 488, 494, 525, 0,
7159 				DRM_MODE_FLAG_INTERLACE),
72
-			.vrefresh = 60,
7360 			.picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3,
7461 		},
7562 	},
....@@ -179,8 +166,13 @@
179166 	struct meson_drm *priv = meson_venc_cvbs->priv;
180167 
181168 	/* Disable CVBS VDAC */
182
-	regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
183
-	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
169
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
170
+		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0);
171
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
172
+	} else {
173
+		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0);
174
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8);
175
+	}
184176 }
185177 
186178 static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
....@@ -190,15 +182,20 @@
190182 	struct meson_drm *priv = meson_venc_cvbs->priv;
191183 
192184 	/* VDAC0 source is not from ATV */
193
-	writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
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+	writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0,
186
+			    priv->io_base + _REG(VENC_VDAC_DACSEL0));
194187 
195
-	if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
188
+	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
196189 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
197
-	else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
198
-		 meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
190
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
191
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
192
+		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
199193 		regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001);
200
-
201
-	regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
194
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0);
195
+	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
196
+		regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001);
197
+		regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0);
198
+	}
202199 }
203200 
204201 static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,
....@@ -214,8 +211,10 @@
214211 		meson_venci_cvbs_mode_set(priv, meson_mode->enci);
215212 
216213 		/* Setup 27MHz vclk2 for ENCI and VDAC */
217
-		meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS, MESON_VCLK_CVBS,
218
-				 MESON_VCLK_CVBS, MESON_VCLK_CVBS, true);
214
+		meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
215
+				 MESON_VCLK_CVBS, MESON_VCLK_CVBS,
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+				 MESON_VCLK_CVBS, MESON_VCLK_CVBS,
217
+				 true);
219218 	}
220219 }
221220