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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/exynos/exynos_drm_scaler.c
..
..
@@ -1,30 +1,27 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * Copyright (C) 2017 Samsung Electronics Co.Ltd
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  * Author:
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- *	Andrzej Pietrasiewicz <andrzej.p@samsung.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundationr
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+ *	Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>
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  */
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7
 
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-#include <linux/kernel.h>
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+#include <linux/clk.h>
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9
 #include <linux/component.h>
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 #include <linux/err.h>
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 #include <linux/interrupt.h>
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 #include <linux/io.h>
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-#include <linux/platform_device.h>
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-#include <linux/clk.h>
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+#include <linux/kernel.h>
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 #include <linux/of_device.h>
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+#include <linux/platform_device.h>
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 #include <linux/pm_runtime.h>
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17
 
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-#include <drm/drmP.h>
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+#include <drm/drm_fourcc.h>
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 #include <drm/exynos_drm.h>
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-#include "regs-scaler.h"
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-#include "exynos_drm_fb.h"
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+
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 #include "exynos_drm_drv.h"
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-#include "exynos_drm_iommu.h"
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+#include "exynos_drm_fb.h"
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 #include "exynos_drm_ipp.h"
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+#include "regs-scaler.h"
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25
 
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 #define scaler_read(offset)		readl(scaler->regs + (offset))
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 #define scaler_write(cfg, offset)	writel(cfg, scaler->regs + (offset))
..
..
@@ -42,6 +39,7 @@
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 struct scaler_context {
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 	struct exynos_drm_ipp		ipp;
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 	struct drm_device		*drm_dev;
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+	void				*dma_priv;
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 	struct device			*dev;
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 	void __iomem			*regs;
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 	struct clk			*clock[SCALER_MAX_CLK];
..
..
@@ -49,56 +47,46 @@
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 	const struct scaler_data	*scaler_data;
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 };
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49
 
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-static u32 scaler_get_format(u32 drm_fmt)
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-{
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-	switch (drm_fmt) {
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-	case DRM_FORMAT_NV12:
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-		return SCALER_YUV420_2P_UV;
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-	case DRM_FORMAT_NV21:
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-		return SCALER_YUV420_2P_VU;
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-	case DRM_FORMAT_YUV420:
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-		return SCALER_YUV420_3P;
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-	case DRM_FORMAT_YUYV:
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-		return SCALER_YUV422_1P_YUYV;
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-	case DRM_FORMAT_UYVY:
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-		return SCALER_YUV422_1P_UYVY;
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-	case DRM_FORMAT_YVYU:
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-		return SCALER_YUV422_1P_YVYU;
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-	case DRM_FORMAT_NV16:
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-		return SCALER_YUV422_2P_UV;
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-	case DRM_FORMAT_NV61:
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-		return SCALER_YUV422_2P_VU;
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-	case DRM_FORMAT_YUV422:
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-		return SCALER_YUV422_3P;
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-	case DRM_FORMAT_NV24:
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-		return SCALER_YUV444_2P_UV;
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-	case DRM_FORMAT_NV42:
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-		return SCALER_YUV444_2P_VU;
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-	case DRM_FORMAT_YUV444:
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-		return SCALER_YUV444_3P;
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-	case DRM_FORMAT_RGB565:
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-		return SCALER_RGB_565;
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-	case DRM_FORMAT_XRGB1555:
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-		return SCALER_ARGB1555;
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-	case DRM_FORMAT_ARGB1555:
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-		return SCALER_ARGB1555;
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-	case DRM_FORMAT_XRGB4444:
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-		return SCALER_ARGB4444;
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-	case DRM_FORMAT_ARGB4444:
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-		return SCALER_ARGB4444;
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-	case DRM_FORMAT_XRGB8888:
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-		return SCALER_ARGB8888;
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-	case DRM_FORMAT_ARGB8888:
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-		return SCALER_ARGB8888;
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-	case DRM_FORMAT_RGBX8888:
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-		return SCALER_RGBA8888;
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-	case DRM_FORMAT_RGBA8888:
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-		return SCALER_RGBA8888;
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-	default:
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-		break;
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-	}
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+struct scaler_format {
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+	u32	drm_fmt;
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+	u32	internal_fmt;
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+	u32	chroma_tile_w;
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+	u32	chroma_tile_h;
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+};
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56
 
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-	return 0;
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+static const struct scaler_format scaler_formats[] = {
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+	{ DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
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+	{ DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
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+	{ DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
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+	{ DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
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+	{ DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
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+	{ DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
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+	{ DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
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+	{ DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
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+	{ DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
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+	{ DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
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+	{ DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
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+	{ DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
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+	{ DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
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+	{ DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
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+	{ DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
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+	{ DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 },
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+	{ DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 },
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+	{ DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 },
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+	{ DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 },
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+	{ DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 },
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+	{ DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 },
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+};
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+
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+static const struct scaler_format *scaler_get_format(u32 drm_fmt)
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+{
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+	int i;
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+
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+	for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
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+		if (scaler_formats[i].drm_fmt == drm_fmt)
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+			return &scaler_formats[i];
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+
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+	return NULL;
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 }
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 static inline int scaler_reset(struct scaler_context *scaler)
..
..
@@ -152,11 +140,11 @@
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 }
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 static inline void scaler_set_src_fmt(struct scaler_context *scaler,
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-	u32 src_fmt)
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+	u32 src_fmt, u32 tile)
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 {
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 	u32 val;
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-	val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt);
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+	val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
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 	scaler_write(val, SCALER_SRC_CFG);
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 }
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150
 
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..
@@ -188,15 +176,20 @@
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 	scaler_write(val, SCALER_SRC_SPAN);
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 }
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178
 
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-static inline void scaler_set_src_luma_pos(struct scaler_context *scaler,
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-	struct drm_exynos_ipp_task_rect *src_pos)
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+static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler,
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+			struct drm_exynos_ipp_task_rect *src_pos,
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+			const struct scaler_format *fmt)
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 {
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 	u32 val;
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 	val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
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 	val |=  SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2);
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 	scaler_write(val, SCALER_SRC_Y_POS);
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-	scaler_write(val, SCALER_SRC_C_POS); /* ATTENTION! */
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+	val = SCALER_SRC_C_POS_SET_CH_POS(
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+		(src_pos->x * fmt->chroma_tile_w / 16) << 2);
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+	val |=  SCALER_SRC_C_POS_SET_CV_POS(
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+		(src_pos->y * fmt->chroma_tile_h / 16) << 2);
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+	scaler_write(val, SCALER_SRC_C_POS);
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 }
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194
 
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 static inline void scaler_set_src_wh(struct scaler_context *scaler,
..
..
@@ -366,11 +359,12 @@
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 	struct scaler_context *scaler =
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 			container_of(ipp, struct scaler_context, ipp);
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361
 
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-	u32 src_fmt = scaler_get_format(task->src.buf.fourcc);
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 	struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect;
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-
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-	u32 dst_fmt = scaler_get_format(task->dst.buf.fourcc);
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 	struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect;
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+	const struct scaler_format *src_fmt, *dst_fmt;
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+
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+	src_fmt = scaler_get_format(task->src.buf.fourcc);
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+	dst_fmt = scaler_get_format(task->dst.buf.fourcc);
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368
 
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 	pm_runtime_get_sync(scaler->dev);
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 	if (scaler_reset(scaler)) {
..
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@@ -380,13 +374,14 @@
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374
 
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 	scaler->task = task;
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376
 
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-	scaler_set_src_fmt(scaler, src_fmt);
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+	scaler_set_src_fmt(
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+		scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0);
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 	scaler_set_src_base(scaler, &task->src);
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 	scaler_set_src_span(scaler, &task->src);
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-	scaler_set_src_luma_pos(scaler, src_pos);
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+	scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt);
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 	scaler_set_src_wh(scaler, src_pos);
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383
 
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-	scaler_set_dst_fmt(scaler, dst_fmt);
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+	scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt);
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 	scaler_set_dst_base(scaler, &task->dst);
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 	scaler_set_dst_span(scaler, &task->dst);
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 	scaler_set_dst_luma_pos(scaler, dst_pos);
..
..
@@ -455,9 +450,10 @@
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450
 	struct exynos_drm_ipp *ipp = &scaler->ipp;
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451
 
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 	scaler->drm_dev = drm_dev;
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-	drm_iommu_attach_device(drm_dev, dev);
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+	ipp->drm_dev = drm_dev;
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+	exynos_drm_register_dma(drm_dev, dev, &scaler->dma_priv);
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455
 
460
-	exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
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+	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
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457
 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
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 			DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
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 			scaler->scaler_data->formats,
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@@ -472,11 +468,11 @@
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468
 			void *data)
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469
 {
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 	struct scaler_context *scaler = dev_get_drvdata(dev);
475
-	struct drm_device *drm_dev = data;
476
471
 	struct exynos_drm_ipp *ipp = &scaler->ipp;
477
472
 
478
-	exynos_drm_ipp_unregister(drm_dev, ipp);
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-	drm_iommu_detach_device(scaler->drm_dev, scaler->dev);
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+	exynos_drm_ipp_unregister(dev, ipp);
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+	exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev,
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+				  &scaler->dma_priv);
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 }
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477
 
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 static const struct component_ops scaler_component_ops = {
..
..
@@ -506,10 +502,8 @@
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 		return PTR_ERR(scaler->regs);
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503
 
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 	irq = platform_get_irq(pdev, 0);
509
-	if (irq < 0) {
510
-		dev_err(dev, "failed to get irq\n");
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+	if (irq < 0)
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 		return irq;
512
-	}
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507
 
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 	ret = devm_request_threaded_irq(dev, irq, NULL,	scaler_irq_handler,
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 					IRQF_ONESHOT, "drm_scaler", scaler);
..
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@@ -617,6 +611,16 @@
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 			  .v = { 65536 * 1 / 4, 65536 * 16 }) },
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 };
619
613
 
614
+static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
615
+	{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
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+	{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
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+	{ IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})},
618
+	{ }
619
+};
620
+
621
+#define IPP_SRCDST_TILE_FORMAT(f, l)	\
622
+	IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l))
623
+
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 static const struct exynos_drm_ipp_formats exynos5420_formats[] = {
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 	/* SCALER_YUV420_2P_UV */
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 	{ IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) },
..
..
@@ -680,6 +684,18 @@
680
684
 
681
685
 	/* SCALER_RGBA8888 */
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 	{ IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) },
687
+
688
+	/* SCALER_YUV420_2P_UV TILE */
689
+	{ IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) },
690
+
691
+	/* SCALER_YUV420_2P_VU TILE */
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+	{ IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) },
693
+
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+	/* SCALER_YUV420_3P TILE */
695
+	{ IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) },
696
+
697
+	/* SCALER_YUV422_1P_YUYV TILE */
698
+	{ IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) },
683
699
 };
684
700
 
685
701
 static const struct scaler_data exynos5420_data = {