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| 33 | 33 | #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 |
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| 34 | 34 | #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL |
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| 35 | 35 | |
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| 36 | +/* DF_CS_UMC_AON0_DfGlobalCtrl */ |
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| 37 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K__SHIFT 0x14 |
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| 38 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M__SHIFT 0x15 |
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| 39 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G__SHIFT 0x16 |
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| 40 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K_MASK 0x00100000L |
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| 41 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M_MASK 0x00200000L |
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| 42 | +#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G_MASK 0x00400000L |
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| 43 | + |
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| 36 | 44 | /* DF_CS_AON0_DramBaseAddress0 */ |
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| 37 | 45 | #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 |
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| 38 | 46 | #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 |
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| .. | .. |
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| 45 | 53 | #define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L |
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| 46 | 54 | #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L |
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| 47 | 55 | |
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| 56 | +//DF_CS_UMC_AON0_DramLimitAddress0 |
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| 57 | +#define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID__SHIFT 0x0 |
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| 58 | +#define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO__SHIFT 0xa |
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| 59 | +#define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr__SHIFT 0xc |
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| 60 | +#define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID_MASK 0x000003FFL |
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| 61 | +#define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO_MASK 0x00000400L |
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| 62 | +#define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr_MASK 0xFFFFF000L |
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| 63 | + |
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| 48 | 64 | #endif |
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