| .. | .. |
|---|
| 43 | 43 | enum dpcd_downstream_port_type { |
|---|
| 44 | 44 | DOWNSTREAM_DP = 0, |
|---|
| 45 | 45 | DOWNSTREAM_VGA, |
|---|
| 46 | | - DOWNSTREAM_DVI_HDMI, |
|---|
| 46 | + DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */ |
|---|
| 47 | 47 | DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ |
|---|
| 48 | 48 | }; |
|---|
| 49 | 49 | |
|---|
| .. | .. |
|---|
| 149 | 149 | PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, |
|---|
| 150 | 150 | }; |
|---|
| 151 | 151 | |
|---|
| 152 | +#define DP_SOURCE_TABLE_REVISION 0x310 |
|---|
| 153 | +#define DP_SOURCE_PAYLOAD_SIZE 0x311 |
|---|
| 154 | +#define DP_SOURCE_SINK_CAP 0x317 |
|---|
| 155 | +#define DP_SOURCE_BACKLIGHT_LEVEL 0x320 |
|---|
| 156 | +#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 |
|---|
| 157 | +#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E |
|---|
| 158 | +#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F |
|---|
| 159 | + |
|---|
| 152 | 160 | #endif /* __DAL_DPCD_DEFS_H__ */ |
|---|