| .. | .. |
|---|
| 23 | 23 | * |
|---|
| 24 | 24 | */ |
|---|
| 25 | 25 | |
|---|
| 26 | +#include <linux/slab.h> |
|---|
| 27 | + |
|---|
| 26 | 28 | #include "dce_ipp.h" |
|---|
| 27 | 29 | #include "reg_helper.h" |
|---|
| 28 | 30 | #include "dm_services.h" |
|---|
| .. | .. |
|---|
| 229 | 231 | CURSOR2_DEGAMMA_MODE, degamma_type); |
|---|
| 230 | 232 | } |
|---|
| 231 | 233 | |
|---|
| 234 | +#if defined(CONFIG_DRM_AMD_DC_SI) |
|---|
| 235 | +static void dce60_ipp_set_degamma( |
|---|
| 236 | + struct input_pixel_processor *ipp, |
|---|
| 237 | + enum ipp_degamma_mode mode) |
|---|
| 238 | +{ |
|---|
| 239 | + struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); |
|---|
| 240 | + uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; |
|---|
| 241 | + |
|---|
| 242 | + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); |
|---|
| 243 | + /* DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL reg */ |
|---|
| 244 | + REG_SET_2(DEGAMMA_CONTROL, 0, |
|---|
| 245 | + GRPH_DEGAMMA_MODE, degamma_type, |
|---|
| 246 | + CURSOR_DEGAMMA_MODE, degamma_type); |
|---|
| 247 | +} |
|---|
| 248 | +#endif |
|---|
| 249 | + |
|---|
| 232 | 250 | static const struct ipp_funcs dce_ipp_funcs = { |
|---|
| 233 | 251 | .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, |
|---|
| 234 | 252 | .ipp_cursor_set_position = dce_ipp_cursor_set_position, |
|---|
| .. | .. |
|---|
| 236 | 254 | .ipp_program_input_lut = dce_ipp_program_input_lut, |
|---|
| 237 | 255 | .ipp_set_degamma = dce_ipp_set_degamma |
|---|
| 238 | 256 | }; |
|---|
| 257 | + |
|---|
| 258 | +#if defined(CONFIG_DRM_AMD_DC_SI) |
|---|
| 259 | +static const struct ipp_funcs dce60_ipp_funcs = { |
|---|
| 260 | + .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes, |
|---|
| 261 | + .ipp_cursor_set_position = dce_ipp_cursor_set_position, |
|---|
| 262 | + .ipp_program_prescale = dce_ipp_program_prescale, |
|---|
| 263 | + .ipp_program_input_lut = dce_ipp_program_input_lut, |
|---|
| 264 | + .ipp_set_degamma = dce60_ipp_set_degamma |
|---|
| 265 | +}; |
|---|
| 266 | +#endif |
|---|
| 267 | + |
|---|
| 239 | 268 | |
|---|
| 240 | 269 | /*****************************************/ |
|---|
| 241 | 270 | /* Constructor, Destructor */ |
|---|
| .. | .. |
|---|
| 258 | 287 | ipp_dce->ipp_mask = ipp_mask; |
|---|
| 259 | 288 | } |
|---|
| 260 | 289 | |
|---|
| 290 | +#if defined(CONFIG_DRM_AMD_DC_SI) |
|---|
| 291 | +void dce60_ipp_construct( |
|---|
| 292 | + struct dce_ipp *ipp_dce, |
|---|
| 293 | + struct dc_context *ctx, |
|---|
| 294 | + int inst, |
|---|
| 295 | + const struct dce_ipp_registers *regs, |
|---|
| 296 | + const struct dce_ipp_shift *ipp_shift, |
|---|
| 297 | + const struct dce_ipp_mask *ipp_mask) |
|---|
| 298 | +{ |
|---|
| 299 | + ipp_dce->base.ctx = ctx; |
|---|
| 300 | + ipp_dce->base.inst = inst; |
|---|
| 301 | + ipp_dce->base.funcs = &dce60_ipp_funcs; |
|---|
| 302 | + |
|---|
| 303 | + ipp_dce->regs = regs; |
|---|
| 304 | + ipp_dce->ipp_shift = ipp_shift; |
|---|
| 305 | + ipp_dce->ipp_mask = ipp_mask; |
|---|
| 306 | +} |
|---|
| 307 | +#endif |
|---|
| 308 | + |
|---|
| 261 | 309 | void dce_ipp_destroy(struct input_pixel_processor **ipp) |
|---|
| 262 | 310 | { |
|---|
| 263 | 311 | kfree(TO_DCE_IPP(*ipp)); |
|---|