forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
....@@ -37,6 +37,8 @@
3737 #include "bios_parser_types_internal2.h"
3838 #include "amdgpu.h"
3939 
40
+#include "dc_dmub_srv.h"
41
+#include "dc.h"
4042 
4143 #define DC_LOGGER \
4244 	bp->base.ctx->logger
....@@ -87,6 +89,10 @@
8789 	struct bios_parser *bp,
8890 	struct bp_encoder_control *cntl);
8991 
92
+static enum bp_result encoder_control_fallback(
93
+	struct bios_parser *bp,
94
+	struct bp_encoder_control *cntl);
95
+
9096 static void init_dig_encoder_control(struct bios_parser *bp)
9197 {
9298 	uint32_t version =
....@@ -98,9 +104,30 @@
98104 		break;
99105 	default:
100106 		dm_output_to_console("Don't have dig_encoder_control for v%d\n", version);
101
-		bp->cmd_tbl.dig_encoder_control = NULL;
107
+		bp->cmd_tbl.dig_encoder_control = encoder_control_fallback;
102108 		break;
103109 	}
110
+}
111
+
112
+static void encoder_control_dmcub(
113
+		struct dc_dmub_srv *dmcub,
114
+		struct dig_encoder_stream_setup_parameters_v1_5 *dig)
115
+{
116
+	union dmub_rb_cmd cmd;
117
+
118
+	memset(&cmd, 0, sizeof(cmd));
119
+
120
+	cmd.digx_encoder_control.header.type = DMUB_CMD__VBIOS;
121
+	cmd.digx_encoder_control.header.sub_type =
122
+		DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL;
123
+	cmd.digx_encoder_control.header.payload_bytes =
124
+		sizeof(cmd.digx_encoder_control) -
125
+		sizeof(cmd.digx_encoder_control.header);
126
+	cmd.digx_encoder_control.encoder_control.dig.stream_param = *dig;
127
+
128
+	dc_dmub_srv_cmd_queue(dmcub, &cmd);
129
+	dc_dmub_srv_cmd_execute(dmcub);
130
+	dc_dmub_srv_wait_idle(dmcub);
104131 }
105132 
106133 static enum bp_result encoder_control_digx_v1_5(
....@@ -155,10 +182,28 @@
155182 			break;
156183 		}
157184 
185
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
186
+	    bp->base.ctx->dc->debug.dmub_command_table) {
187
+		encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);
188
+		return BP_RESULT_OK;
189
+	}
190
+
158191 	if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params))
159192 		result = BP_RESULT_OK;
160193 
161194 	return result;
195
+}
196
+
197
+static enum bp_result encoder_control_fallback(
198
+	struct bios_parser *bp,
199
+	struct bp_encoder_control *cntl)
200
+{
201
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
202
+	    bp->base.ctx->dc->debug.dmub_command_table) {
203
+		return encoder_control_digx_v1_5(bp, cntl);
204
+	}
205
+
206
+	return BP_RESULT_FAILURE;
162207 }
163208 
164209 /*****************************************************************************
....@@ -173,22 +218,47 @@
173218 	struct bios_parser *bp,
174219 	struct bp_transmitter_control *cntl);
175220 
221
+static enum bp_result transmitter_control_fallback(
222
+	struct bios_parser *bp,
223
+	struct bp_transmitter_control *cntl);
224
+
176225 static void init_transmitter_control(struct bios_parser *bp)
177226 {
178227 	uint8_t frev;
179228 	uint8_t crev;
180229 
181
-	if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
182
-		BREAK_TO_DEBUGGER();
230
+	BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev);
231
+
183232 	switch (crev) {
184233 	case 6:
185234 		bp->cmd_tbl.transmitter_control = transmitter_control_v1_6;
186235 		break;
187236 	default:
188237 		dm_output_to_console("Don't have transmitter_control for v%d\n", crev);
189
-		bp->cmd_tbl.transmitter_control = NULL;
238
+		bp->cmd_tbl.transmitter_control = transmitter_control_fallback;
190239 		break;
191240 	}
241
+}
242
+
243
+static void transmitter_control_dmcub(
244
+		struct dc_dmub_srv *dmcub,
245
+		struct dig_transmitter_control_parameters_v1_6 *dig)
246
+{
247
+	union dmub_rb_cmd cmd;
248
+
249
+	memset(&cmd, 0, sizeof(cmd));
250
+
251
+	cmd.dig1_transmitter_control.header.type = DMUB_CMD__VBIOS;
252
+	cmd.dig1_transmitter_control.header.sub_type =
253
+		DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL;
254
+	cmd.dig1_transmitter_control.header.payload_bytes =
255
+		sizeof(cmd.dig1_transmitter_control) -
256
+		sizeof(cmd.dig1_transmitter_control.header);
257
+	cmd.dig1_transmitter_control.transmitter_control.dig = *dig;
258
+
259
+	dc_dmub_srv_cmd_queue(dmcub, &cmd);
260
+	dc_dmub_srv_cmd_execute(dmcub);
261
+	dc_dmub_srv_wait_idle(dmcub);
192262 }
193263 
194264 static enum bp_result transmitter_control_v1_6(
....@@ -222,11 +292,28 @@
222292 		__func__, ps.param.symclk_10khz);
223293 	}
224294 
295
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
296
+	    bp->base.ctx->dc->debug.dmub_command_table) {
297
+		transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);
298
+		return BP_RESULT_OK;
299
+	}
225300 
226301 /*color_depth not used any more, driver has deep color factor in the Phyclk*/
227302 	if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps))
228303 		result = BP_RESULT_OK;
229304 	return result;
305
+}
306
+
307
+static enum bp_result transmitter_control_fallback(
308
+	struct bios_parser *bp,
309
+	struct bp_transmitter_control *cntl)
310
+{
311
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
312
+	    bp->base.ctx->dc->debug.dmub_command_table) {
313
+		return transmitter_control_v1_6(bp, cntl);
314
+	}
315
+
316
+	return BP_RESULT_FAILURE;
230317 }
231318 
232319 /******************************************************************************
....@@ -241,6 +328,10 @@
241328 	struct bios_parser *bp,
242329 	struct bp_pixel_clock_parameters *bp_params);
243330 
331
+static enum bp_result set_pixel_clock_fallback(
332
+	struct bios_parser *bp,
333
+	struct bp_pixel_clock_parameters *bp_params);
334
+
244335 static void init_set_pixel_clock(struct bios_parser *bp)
245336 {
246337 	switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) {
....@@ -250,12 +341,30 @@
250341 	default:
251342 		dm_output_to_console("Don't have set_pixel_clock for v%d\n",
252343 			 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock));
253
-		bp->cmd_tbl.set_pixel_clock = NULL;
344
+		bp->cmd_tbl.set_pixel_clock = set_pixel_clock_fallback;
254345 		break;
255346 	}
256347 }
257348 
349
+static void set_pixel_clock_dmcub(
350
+		struct dc_dmub_srv *dmcub,
351
+		struct set_pixel_clock_parameter_v1_7 *clk)
352
+{
353
+	union dmub_rb_cmd cmd;
258354 
355
+	memset(&cmd, 0, sizeof(cmd));
356
+
357
+	cmd.set_pixel_clock.header.type = DMUB_CMD__VBIOS;
358
+	cmd.set_pixel_clock.header.sub_type = DMUB_CMD__VBIOS_SET_PIXEL_CLOCK;
359
+	cmd.set_pixel_clock.header.payload_bytes =
360
+		sizeof(cmd.set_pixel_clock) -
361
+		sizeof(cmd.set_pixel_clock.header);
362
+	cmd.set_pixel_clock.pixel_clock.clk = *clk;
363
+
364
+	dc_dmub_srv_cmd_queue(dmcub, &cmd);
365
+	dc_dmub_srv_cmd_execute(dmcub);
366
+	dc_dmub_srv_wait_idle(dmcub);
367
+}
259368 
260369 static enum bp_result set_pixel_clock_v7(
261370 	struct bios_parser *bp,
....@@ -301,17 +410,17 @@
301410 			cmd_helper->encoder_mode_bp_to_atom(
302411 				bp_params->signal_type, false);
303412 
304
-		/* We need to convert from KHz units into 10KHz units */
305
-		clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock *
306
-				10);
413
+		clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
307414 
308415 		clk.deep_color_ratio =
309416 			(uint8_t) bp->cmd_helper->
310417 				transmitter_color_depth_to_atom(
311418 					bp_params->color_depth);
312
-		DC_LOG_BIOS("%s:program display clock = %d"\
313
-				"colorDepth = %d\n", __func__,\
314
-				bp_params->target_pixel_clock, bp_params->color_depth);
419
+
420
+		DC_LOG_BIOS("%s:program display clock = %d, tg = %d, pll = %d, "\
421
+				"colorDepth = %d\n", __func__,
422
+				bp_params->target_pixel_clock_100hz, (int)controller_id,
423
+				pll_id, bp_params->color_depth);
315424 
316425 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
317426 			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
....@@ -331,10 +440,28 @@
331440 		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
332441 			clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
333442 
443
+		if (bp->base.ctx->dc->ctx->dmub_srv &&
444
+		    bp->base.ctx->dc->debug.dmub_command_table) {
445
+			set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);
446
+			return BP_RESULT_OK;
447
+		}
448
+
334449 		if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk))
335450 			result = BP_RESULT_OK;
336451 	}
337452 	return result;
453
+}
454
+
455
+static enum bp_result set_pixel_clock_fallback(
456
+	struct bios_parser *bp,
457
+	struct bp_pixel_clock_parameters *bp_params)
458
+{
459
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
460
+	    bp->base.ctx->dc->debug.dmub_command_table) {
461
+		return set_pixel_clock_v7(bp, bp_params);
462
+	}
463
+
464
+	return BP_RESULT_FAILURE;
338465 }
339466 
340467 /******************************************************************************
....@@ -442,10 +569,7 @@
442569 			 * but it is 4 either from Edid data (spec CEA 861)
443570 			 * or CEA timing table.
444571 			 */
445
-			params.v_syncoffset =
446
-				cpu_to_le16(le16_to_cpu(params.v_syncoffset) +
447
-						1);
448
-
572
+			le16_add_cpu(&params.v_syncoffset, 1);
449573 		}
450574 	}
451575 
....@@ -455,75 +579,6 @@
455579 					0x100); /* ATOM_DOUBLE_CLOCK_MODE */
456580 
457581 	if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params))
458
-		result = BP_RESULT_OK;
459
-
460
-	return result;
461
-}
462
-
463
-/******************************************************************************
464
- ******************************************************************************
465
- **
466
- **                  SELECT CRTC SOURCE
467
- **
468
- ******************************************************************************
469
- *****************************************************************************/
470
-
471
-
472
-static enum bp_result select_crtc_source_v3(
473
-	struct bios_parser *bp,
474
-	struct bp_crtc_source_select *bp_params);
475
-
476
-static void init_select_crtc_source(struct bios_parser *bp)
477
-{
478
-	switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {
479
-	case 3:
480
-		bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
481
-		break;
482
-	default:
483
-		dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
484
-			 BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source));
485
-		bp->cmd_tbl.select_crtc_source = NULL;
486
-		break;
487
-	}
488
-}
489
-
490
-
491
-static enum bp_result select_crtc_source_v3(
492
-	struct bios_parser *bp,
493
-	struct bp_crtc_source_select *bp_params)
494
-{
495
-	bool result = BP_RESULT_FAILURE;
496
-	struct select_crtc_source_parameters_v2_3 params;
497
-	uint8_t atom_controller_id;
498
-	uint32_t atom_engine_id;
499
-	enum signal_type s = bp_params->signal;
500
-
501
-	memset(&params, 0, sizeof(params));
502
-
503
-	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
504
-			&atom_controller_id))
505
-		params.crtc_id = atom_controller_id;
506
-	else
507
-		return result;
508
-
509
-	if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
510
-			&atom_engine_id))
511
-		params.encoder_id = (uint8_t)atom_engine_id;
512
-	else
513
-		return result;
514
-
515
-	if (s == SIGNAL_TYPE_EDP ||
516
-		(s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal ==
517
-							SIGNAL_TYPE_LVDS))
518
-		s = SIGNAL_TYPE_LVDS;
519
-
520
-	params.encode_mode =
521
-			bp->cmd_helper->encoder_mode_bp_to_atom(
522
-					s, bp_params->enable_dp_audio);
523
-	/* Needed for VBIOS Random Spatial Dithering feature */
524
-	params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth);
525
-
526
-	if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params))
527582 		result = BP_RESULT_OK;
528583 
529584 	return result;
....@@ -638,6 +693,11 @@
638693 	enum controller_id crtc_id,
639694 	enum bp_pipe_control_action action);
640695 
696
+static enum bp_result enable_disp_power_gating_fallback(
697
+	struct bios_parser *bp,
698
+	enum controller_id crtc_id,
699
+	enum bp_pipe_control_action action);
700
+
641701 static void init_enable_disp_power_gating(
642702 	struct bios_parser *bp)
643703 {
....@@ -649,9 +709,30 @@
649709 	default:
650710 		dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n",
651711 			 BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating));
652
-		bp->cmd_tbl.enable_disp_power_gating = NULL;
712
+		bp->cmd_tbl.enable_disp_power_gating = enable_disp_power_gating_fallback;
653713 		break;
654714 	}
715
+}
716
+
717
+static void enable_disp_power_gating_dmcub(
718
+	struct dc_dmub_srv *dmcub,
719
+	struct enable_disp_power_gating_parameters_v2_1 *pwr)
720
+{
721
+	union dmub_rb_cmd cmd;
722
+
723
+	memset(&cmd, 0, sizeof(cmd));
724
+
725
+	cmd.enable_disp_power_gating.header.type = DMUB_CMD__VBIOS;
726
+	cmd.enable_disp_power_gating.header.sub_type =
727
+		DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING;
728
+	cmd.enable_disp_power_gating.header.payload_bytes =
729
+		sizeof(cmd.enable_disp_power_gating) -
730
+		sizeof(cmd.enable_disp_power_gating.header);
731
+	cmd.enable_disp_power_gating.power_gating.pwr = *pwr;
732
+
733
+	dc_dmub_srv_cmd_queue(dmcub, &cmd);
734
+	dc_dmub_srv_cmd_execute(dmcub);
735
+	dc_dmub_srv_wait_idle(dmcub);
655736 }
656737 
657738 static enum bp_result enable_disp_power_gating_v2_1(
....@@ -673,10 +754,30 @@
673754 	ps.param.enable =
674755 		bp->cmd_helper->disp_power_gating_action_to_atom(action);
675756 
757
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
758
+	    bp->base.ctx->dc->debug.dmub_command_table) {
759
+		enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,
760
+					       &ps.param);
761
+		return BP_RESULT_OK;
762
+	}
763
+
676764 	if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param))
677765 		result = BP_RESULT_OK;
678766 
679767 	return result;
768
+}
769
+
770
+static enum bp_result enable_disp_power_gating_fallback(
771
+	struct bios_parser *bp,
772
+	enum controller_id crtc_id,
773
+	enum bp_pipe_control_action action)
774
+{
775
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
776
+	    bp->base.ctx->dc->debug.dmub_command_table) {
777
+		return enable_disp_power_gating_v2_1(bp, crtc_id, action);
778
+	}
779
+
780
+	return BP_RESULT_FAILURE;
680781 }
681782 
682783 /******************************************************************************
....@@ -800,6 +901,61 @@
800901 	return 0;
801902 }
802903 
904
+/******************************************************************************
905
+ ******************************************************************************
906
+ **
907
+ **                  LVTMA CONTROL
908
+ **
909
+ ******************************************************************************
910
+ *****************************************************************************/
911
+
912
+static enum bp_result enable_lvtma_control(
913
+	struct bios_parser *bp,
914
+	uint8_t uc_pwr_on);
915
+
916
+static void init_enable_lvtma_control(struct bios_parser *bp)
917
+{
918
+	/* TODO add switch for table vrsion */
919
+	bp->cmd_tbl.enable_lvtma_control = enable_lvtma_control;
920
+
921
+}
922
+
923
+static void enable_lvtma_control_dmcub(
924
+	struct dc_dmub_srv *dmcub,
925
+	uint8_t uc_pwr_on)
926
+{
927
+
928
+	union dmub_rb_cmd cmd;
929
+
930
+	memset(&cmd, 0, sizeof(cmd));
931
+
932
+	cmd.cmd_common.header.type = DMUB_CMD__VBIOS;
933
+	cmd.cmd_common.header.sub_type =
934
+			DMUB_CMD__VBIOS_LVTMA_CONTROL;
935
+	cmd.cmd_common.cmd_buffer[0] =
936
+			uc_pwr_on;
937
+
938
+	dc_dmub_srv_cmd_queue(dmcub, &cmd);
939
+	dc_dmub_srv_cmd_execute(dmcub);
940
+	dc_dmub_srv_wait_idle(dmcub);
941
+
942
+}
943
+
944
+static enum bp_result enable_lvtma_control(
945
+	struct bios_parser *bp,
946
+	uint8_t uc_pwr_on)
947
+{
948
+	enum bp_result result = BP_RESULT_FAILURE;
949
+
950
+	if (bp->base.ctx->dc->ctx->dmub_srv &&
951
+	    bp->base.ctx->dc->debug.dmub_command_table) {
952
+		enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv,
953
+				uc_pwr_on);
954
+		return BP_RESULT_OK;
955
+	}
956
+	return result;
957
+}
958
+
803959 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
804960 {
805961 	init_dig_encoder_control(bp);
....@@ -808,7 +964,6 @@
808964 
809965 	init_set_crtc_timing(bp);
810966 
811
-	init_select_crtc_source(bp);
812967 	init_enable_crtc(bp);
813968 
814969 	init_external_encoder_control(bp);
....@@ -816,4 +971,5 @@
816971 	init_set_dce_clock(bp);
817972 	init_get_smu_clock_info(bp);
818973 
974
+	init_enable_lvtma_control(bp);
819975 }