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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
..
..
@@ -26,24 +26,37 @@
26
26
 
27
27
 #include <linux/firmware.h>
28
28
 #include <linux/module.h>
29
-#include <drm/drmP.h>
30
-#include <drm/drm.h>
29
+#include <linux/pci.h>
31
30
 
32
31
 #include "amdgpu.h"
33
32
 #include "amdgpu_pm.h"
34
33
 #include "amdgpu_vcn.h"
35
34
 #include "soc15d.h"
36
-#include "soc15_common.h"
37
-
38
-#include "vcn/vcn_1_0_offset.h"
39
-
40
-/* 1 second timeout */
41
-#define VCN_IDLE_TIMEOUT	msecs_to_jiffies(1000)
42
35
 
43
36
 /* Firmware Names */
44
37
 #define FIRMWARE_RAVEN		"amdgpu/raven_vcn.bin"
38
+#define FIRMWARE_PICASSO	"amdgpu/picasso_vcn.bin"
39
+#define FIRMWARE_RAVEN2		"amdgpu/raven2_vcn.bin"
40
+#define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
41
+#define FIRMWARE_RENOIR 	"amdgpu/renoir_vcn.bin"
42
+#define FIRMWARE_GREEN_SARDINE 	"amdgpu/green_sardine_vcn.bin"
43
+#define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
44
+#define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
45
+#define FIRMWARE_NAVI12 	"amdgpu/navi12_vcn.bin"
46
+#define FIRMWARE_SIENNA_CICHLID 	"amdgpu/sienna_cichlid_vcn.bin"
47
+#define FIRMWARE_NAVY_FLOUNDER 	"amdgpu/navy_flounder_vcn.bin"
45
48
 
46
49
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
50
+MODULE_FIRMWARE(FIRMWARE_PICASSO);
51
+MODULE_FIRMWARE(FIRMWARE_RAVEN2);
52
+MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
53
+MODULE_FIRMWARE(FIRMWARE_RENOIR);
54
+MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
55
+MODULE_FIRMWARE(FIRMWARE_NAVI10);
56
+MODULE_FIRMWARE(FIRMWARE_NAVI14);
57
+MODULE_FIRMWARE(FIRMWARE_NAVI12);
58
+MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
59
+MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
47
60
 
48
61
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
49
62
 
..
..
@@ -53,13 +66,69 @@
53
66
 	const char *fw_name;
54
67
 	const struct common_firmware_header *hdr;
55
68
 	unsigned char fw_check;
56
-	int r;
69
+	int i, r;
57
70
 
58
71
 	INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
72
+	mutex_init(&adev->vcn.vcn_pg_lock);
73
+	mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
74
+	atomic_set(&adev->vcn.total_submission_cnt, 0);
75
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++)
76
+		atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
59
77
 
60
78
 	switch (adev->asic_type) {
61
79
 	case CHIP_RAVEN:
62
-		fw_name = FIRMWARE_RAVEN;
80
+		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
81
+			fw_name = FIRMWARE_RAVEN2;
82
+		else if (adev->apu_flags & AMD_APU_IS_PICASSO)
83
+			fw_name = FIRMWARE_PICASSO;
84
+		else
85
+			fw_name = FIRMWARE_RAVEN;
86
+		break;
87
+	case CHIP_ARCTURUS:
88
+		fw_name = FIRMWARE_ARCTURUS;
89
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
90
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
91
+			adev->vcn.indirect_sram = true;
92
+		break;
93
+	case CHIP_RENOIR:
94
+		if (adev->apu_flags & AMD_APU_IS_RENOIR)
95
+			fw_name = FIRMWARE_RENOIR;
96
+		else
97
+			fw_name = FIRMWARE_GREEN_SARDINE;
98
+
99
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
100
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
101
+			adev->vcn.indirect_sram = true;
102
+		break;
103
+	case CHIP_NAVI10:
104
+		fw_name = FIRMWARE_NAVI10;
105
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
106
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
107
+			adev->vcn.indirect_sram = true;
108
+		break;
109
+	case CHIP_NAVI14:
110
+		fw_name = FIRMWARE_NAVI14;
111
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
112
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
113
+			adev->vcn.indirect_sram = true;
114
+		break;
115
+	case CHIP_NAVI12:
116
+		fw_name = FIRMWARE_NAVI12;
117
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
118
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
119
+			adev->vcn.indirect_sram = true;
120
+		break;
121
+	case CHIP_SIENNA_CICHLID:
122
+		fw_name = FIRMWARE_SIENNA_CICHLID;
123
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
124
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
125
+			adev->vcn.indirect_sram = true;
126
+		break;
127
+	case CHIP_NAVY_FLOUNDER:
128
+		fw_name = FIRMWARE_NAVY_FLOUNDER;
129
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
130
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
131
+			adev->vcn.indirect_sram = true;
63
132
 		break;
64
133
 	default:
65
134
 		return -EINVAL;
..
..
@@ -111,16 +180,37 @@
111
180
 			version_major, version_minor, family_id);
112
181
 	}
113
182
 
114
-	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
115
-		  +  AMDGPU_VCN_SESSION_SIZE * 40;
183
+	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
116
184
 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
117
185
 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
118
-	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
119
-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
120
-				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
121
-	if (r) {
122
-		dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
123
-		return r;
186
+	bo_size += AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
187
+
188
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
189
+		if (adev->vcn.harvest_config & (1 << i))
190
+			continue;
191
+
192
+		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
193
+						AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
194
+						&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
195
+		if (r) {
196
+			dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
197
+			return r;
198
+		}
199
+
200
+		adev->vcn.inst[i].fw_shared_cpu_addr = adev->vcn.inst[i].cpu_addr +
201
+				bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
202
+		adev->vcn.inst[i].fw_shared_gpu_addr = adev->vcn.inst[i].gpu_addr +
203
+				bo_size - AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
204
+
205
+		if (adev->vcn.indirect_sram) {
206
+			r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
207
+					AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
208
+					&adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
209
+			if (r) {
210
+				dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
211
+				return r;
212
+			}
213
+		}
124
214
 	}
125
215
 
126
216
 	return 0;
..
..
@@ -128,22 +218,34 @@
128
218
 
129
219
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
130
220
 {
131
-	int i;
221
+	int i, j;
132
222
 
133
-	kvfree(adev->vcn.saved_bo);
223
+	cancel_delayed_work_sync(&adev->vcn.idle_work);
134
224
 
135
-	amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
136
-			      &adev->vcn.gpu_addr,
137
-			      (void **)&adev->vcn.cpu_addr);
225
+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
226
+		if (adev->vcn.harvest_config & (1 << j))
227
+			continue;
138
228
 
139
-	amdgpu_ring_fini(&adev->vcn.ring_dec);
229
+		if (adev->vcn.indirect_sram) {
230
+			amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
231
+						  &adev->vcn.inst[j].dpg_sram_gpu_addr,
232
+						  (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
233
+		}
234
+		kvfree(adev->vcn.inst[j].saved_bo);
140
235
 
141
-	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
142
-		amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
236
+		amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
237
+					  &adev->vcn.inst[j].gpu_addr,
238
+					  (void **)&adev->vcn.inst[j].cpu_addr);
143
239
 
144
-	amdgpu_ring_fini(&adev->vcn.ring_jpeg);
240
+		amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
241
+
242
+		for (i = 0; i < adev->vcn.num_enc_rings; ++i)
243
+			amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
244
+	}
145
245
 
146
246
 	release_firmware(adev->vcn.fw);
247
+	mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
248
+	mutex_destroy(&adev->vcn.vcn_pg_lock);
147
249
 
148
250
 	return 0;
149
251
 }
..
..
@@ -152,21 +254,25 @@
152
254
 {
153
255
 	unsigned size;
154
256
 	void *ptr;
257
+	int i;
155
258
 
156
259
 	cancel_delayed_work_sync(&adev->vcn.idle_work);
157
260
 
158
-	if (adev->vcn.vcpu_bo == NULL)
159
-		return 0;
261
+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
262
+		if (adev->vcn.harvest_config & (1 << i))
263
+			continue;
264
+		if (adev->vcn.inst[i].vcpu_bo == NULL)
265
+			return 0;
160
266
 
161
-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
162
-	ptr = adev->vcn.cpu_addr;
267
+		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
268
+		ptr = adev->vcn.inst[i].cpu_addr;
163
269
 
164
-	adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
165
-	if (!adev->vcn.saved_bo)
166
-		return -ENOMEM;
270
+		adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
271
+		if (!adev->vcn.inst[i].saved_bo)
272
+			return -ENOMEM;
167
273
 
168
-	memcpy_fromio(adev->vcn.saved_bo, ptr, size);
169
-
274
+		memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
275
+	}
170
276
 	return 0;
171
277
 }
172
278
 
..
..
@@ -174,32 +280,36 @@
174
280
 {
175
281
 	unsigned size;
176
282
 	void *ptr;
283
+	int i;
177
284
 
178
-	if (adev->vcn.vcpu_bo == NULL)
179
-		return -EINVAL;
285
+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
286
+		if (adev->vcn.harvest_config & (1 << i))
287
+			continue;
288
+		if (adev->vcn.inst[i].vcpu_bo == NULL)
289
+			return -EINVAL;
180
290
 
181
-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
182
-	ptr = adev->vcn.cpu_addr;
291
+		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
292
+		ptr = adev->vcn.inst[i].cpu_addr;
183
293
 
184
-	if (adev->vcn.saved_bo != NULL) {
185
-		memcpy_toio(ptr, adev->vcn.saved_bo, size);
186
-		kvfree(adev->vcn.saved_bo);
187
-		adev->vcn.saved_bo = NULL;
188
-	} else {
189
-		const struct common_firmware_header *hdr;
190
-		unsigned offset;
294
+		if (adev->vcn.inst[i].saved_bo != NULL) {
295
+			memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
296
+			kvfree(adev->vcn.inst[i].saved_bo);
297
+			adev->vcn.inst[i].saved_bo = NULL;
298
+		} else {
299
+			const struct common_firmware_header *hdr;
300
+			unsigned offset;
191
301
 
192
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
193
-		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
194
-			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
195
-			memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
196
-				    le32_to_cpu(hdr->ucode_size_bytes));
197
-			size -= le32_to_cpu(hdr->ucode_size_bytes);
198
-			ptr += le32_to_cpu(hdr->ucode_size_bytes);
302
+			hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
303
+			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
304
+				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
305
+				memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
306
+					    le32_to_cpu(hdr->ucode_size_bytes));
307
+				size -= le32_to_cpu(hdr->ucode_size_bytes);
308
+				ptr += le32_to_cpu(hdr->ucode_size_bytes);
309
+			}
310
+			memset_io(ptr, 0, size);
199
311
 		}
200
-		memset_io(ptr, 0, size);
201
312
 	}
202
-
203
313
 	return 0;
204
314
 }
205
315
 
..
..
@@ -207,21 +317,36 @@
207
317
 {
208
318
 	struct amdgpu_device *adev =
209
319
 		container_of(work, struct amdgpu_device, vcn.idle_work.work);
210
-	unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
211
-	unsigned i;
320
+	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
321
+	unsigned int i, j;
212
322
 
213
-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
214
-		fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
323
+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
324
+		if (adev->vcn.harvest_config & (1 << j))
325
+			continue;
326
+
327
+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
328
+			fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
329
+		}
330
+
331
+		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
332
+			struct dpg_pause_state new_state;
333
+
334
+			if (fence[j] ||
335
+				unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
336
+				new_state.fw_based = VCN_DPG_STATE__PAUSE;
337
+			else
338
+				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
339
+
340
+			adev->vcn.pause_dpg_mode(adev, j, &new_state);
341
+		}
342
+
343
+		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
344
+		fences += fence[j];
215
345
 	}
216
346
 
217
-	fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
218
-
219
-	if (fences == 0) {
220
-		if (adev->pm.dpm_enabled)
221
-			amdgpu_dpm_enable_uvd(adev, false);
222
-		else
223
-			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
224
-							       AMD_PG_STATE_GATE);
347
+	if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
348
+		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
349
+		       AMD_PG_STATE_GATE);
225
350
 	} else {
226
351
 		schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
227
352
 	}
..
..
@@ -230,19 +355,46 @@
230
355
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
231
356
 {
232
357
 	struct amdgpu_device *adev = ring->adev;
233
-	bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
234
358
 
235
-	if (set_clocks) {
236
-		if (adev->pm.dpm_enabled)
237
-			amdgpu_dpm_enable_uvd(adev, true);
238
-		else
239
-			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
240
-							       AMD_PG_STATE_UNGATE);
359
+	atomic_inc(&adev->vcn.total_submission_cnt);
360
+	cancel_delayed_work_sync(&adev->vcn.idle_work);
361
+
362
+	mutex_lock(&adev->vcn.vcn_pg_lock);
363
+	amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
364
+	       AMD_PG_STATE_UNGATE);
365
+
366
+	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
367
+		struct dpg_pause_state new_state;
368
+
369
+		if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
370
+			atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
371
+			new_state.fw_based = VCN_DPG_STATE__PAUSE;
372
+		} else {
373
+			unsigned int fences = 0;
374
+			unsigned int i;
375
+
376
+			for (i = 0; i < adev->vcn.num_enc_rings; ++i)
377
+				fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
378
+
379
+			if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
380
+				new_state.fw_based = VCN_DPG_STATE__PAUSE;
381
+			else
382
+				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
383
+		}
384
+
385
+		adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
241
386
 	}
387
+	mutex_unlock(&adev->vcn.vcn_pg_lock);
242
388
 }
243
389
 
244
390
 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
245
391
 {
392
+	if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
393
+		ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
394
+		atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
395
+
396
+	atomic_dec(&ring->adev->vcn.total_submission_cnt);
397
+
246
398
 	schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
247
399
 }
248
400
 
..
..
@@ -253,32 +405,27 @@
253
405
 	unsigned i;
254
406
 	int r;
255
407
 
256
-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
408
+	/* VCN in SRIOV does not support direct register read/write */
409
+	if (amdgpu_sriov_vf(adev))
410
+		return 0;
411
+
412
+	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
257
413
 	r = amdgpu_ring_alloc(ring, 3);
258
-	if (r) {
259
-		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
260
-			  ring->idx, r);
414
+	if (r)
261
415
 		return r;
262
-	}
263
-	amdgpu_ring_write(ring,
264
-		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
416
+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
265
417
 	amdgpu_ring_write(ring, 0xDEADBEEF);
266
418
 	amdgpu_ring_commit(ring);
267
419
 	for (i = 0; i < adev->usec_timeout; i++) {
268
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
420
+		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
269
421
 		if (tmp == 0xDEADBEEF)
270
422
 			break;
271
-		DRM_UDELAY(1);
423
+		udelay(1);
272
424
 	}
273
425
 
274
-	if (i < adev->usec_timeout) {
275
-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
276
-			 ring->idx, i);
277
-	} else {
278
-		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
279
-			  ring->idx, tmp);
280
-		r = -EINVAL;
281
-	}
426
+	if (i >= adev->usec_timeout)
427
+		r = -ETIMEDOUT;
428
+
282
429
 	return r;
283
430
 }
284
431
 
..
..
@@ -293,20 +440,21 @@
293
440
 	uint64_t addr;
294
441
 	int i, r;
295
442
 
296
-	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
443
+	r = amdgpu_job_alloc_with_ib(adev, 64,
444
+					AMDGPU_IB_POOL_DIRECT, &job);
297
445
 	if (r)
298
446
 		goto err;
299
447
 
300
448
 	ib = &job->ibs[0];
301
449
 	addr = amdgpu_bo_gpu_offset(bo);
302
-	ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0);
450
+	ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
303
451
 	ib->ptr[1] = addr;
304
-	ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0);
452
+	ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
305
453
 	ib->ptr[3] = addr >> 32;
306
-	ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0);
454
+	ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
307
455
 	ib->ptr[5] = 0;
308
456
 	for (i = 6; i < 16; i += 2) {
309
-		ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0);
457
+		ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
310
458
 		ib->ptr[i+1] = 0;
311
459
 	}
312
460
 	ib->length_dw = 16;
..
..
@@ -400,30 +548,20 @@
400
548
 	long r;
401
549
 
402
550
 	r = amdgpu_vcn_dec_get_create_msg(ring, 1, NULL);
403
-	if (r) {
404
-		DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
551
+	if (r)
405
552
 		goto error;
406
-	}
407
553
 
408
554
 	r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &fence);
409
-	if (r) {
410
-		DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
555
+	if (r)
411
556
 		goto error;
412
-	}
413
557
 
414
558
 	r = dma_fence_wait_timeout(fence, false, timeout);
415
-	if (r == 0) {
416
-		DRM_ERROR("amdgpu: IB test timed out.\n");
559
+	if (r == 0)
417
560
 		r = -ETIMEDOUT;
418
-	} else if (r < 0) {
419
-		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
420
-	} else {
421
-		DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
561
+	else if (r > 0)
422
562
 		r = 0;
423
-	}
424
563
 
425
564
 	dma_fence_put(fence);
426
-
427
565
 error:
428
566
 	return r;
429
567
 }
..
..
@@ -435,12 +573,12 @@
435
573
 	unsigned i;
436
574
 	int r;
437
575
 
576
+	if (amdgpu_sriov_vf(adev))
577
+		return 0;
578
+
438
579
 	r = amdgpu_ring_alloc(ring, 16);
439
-	if (r) {
440
-		DRM_ERROR("amdgpu: vcn enc failed to lock ring %d (%d).\n",
441
-			  ring->idx, r);
580
+	if (r)
442
581
 		return r;
443
-	}
444
582
 
445
583
 	rptr = amdgpu_ring_get_rptr(ring);
446
584
 
..
..
@@ -450,44 +588,40 @@
450
588
 	for (i = 0; i < adev->usec_timeout; i++) {
451
589
 		if (amdgpu_ring_get_rptr(ring) != rptr)
452
590
 			break;
453
-		DRM_UDELAY(1);
591
+		udelay(1);
454
592
 	}
455
593
 
456
-	if (i < adev->usec_timeout) {
457
-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
458
-			 ring->idx, i);
459
-	} else {
460
-		DRM_ERROR("amdgpu: ring %d test failed\n",
461
-			  ring->idx);
594
+	if (i >= adev->usec_timeout)
462
595
 		r = -ETIMEDOUT;
463
-	}
464
596
 
465
597
 	return r;
466
598
 }
467
599
 
468
600
 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
469
-			      struct dma_fence **fence)
601
+					 struct amdgpu_bo *bo,
602
+					 struct dma_fence **fence)
470
603
 {
471
604
 	const unsigned ib_size_dw = 16;
472
605
 	struct amdgpu_job *job;
473
606
 	struct amdgpu_ib *ib;
474
607
 	struct dma_fence *f = NULL;
475
-	uint64_t dummy;
608
+	uint64_t addr;
476
609
 	int i, r;
477
610
 
478
-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
611
+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
612
+					AMDGPU_IB_POOL_DIRECT, &job);
479
613
 	if (r)
480
614
 		return r;
481
615
 
482
616
 	ib = &job->ibs[0];
483
-	dummy = ib->gpu_addr + 1024;
617
+	addr = amdgpu_bo_gpu_offset(bo);
484
618
 
485
619
 	ib->length_dw = 0;
486
620
 	ib->ptr[ib->length_dw++] = 0x00000018;
487
621
 	ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
488
622
 	ib->ptr[ib->length_dw++] = handle;
489
-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
490
-	ib->ptr[ib->length_dw++] = dummy;
623
+	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
624
+	ib->ptr[ib->length_dw++] = addr;
491
625
 	ib->ptr[ib->length_dw++] = 0x0000000b;
492
626
 
493
627
 	ib->ptr[ib->length_dw++] = 0x00000014;
..
..
@@ -518,28 +652,30 @@
518
652
 }
519
653
 
520
654
 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
521
-				struct dma_fence **fence)
655
+					  struct amdgpu_bo *bo,
656
+					  struct dma_fence **fence)
522
657
 {
523
658
 	const unsigned ib_size_dw = 16;
524
659
 	struct amdgpu_job *job;
525
660
 	struct amdgpu_ib *ib;
526
661
 	struct dma_fence *f = NULL;
527
-	uint64_t dummy;
662
+	uint64_t addr;
528
663
 	int i, r;
529
664
 
530
-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
665
+	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4,
666
+					AMDGPU_IB_POOL_DIRECT, &job);
531
667
 	if (r)
532
668
 		return r;
533
669
 
534
670
 	ib = &job->ibs[0];
535
-	dummy = ib->gpu_addr + 1024;
671
+	addr = amdgpu_bo_gpu_offset(bo);
536
672
 
537
673
 	ib->length_dw = 0;
538
674
 	ib->ptr[ib->length_dw++] = 0x00000018;
539
675
 	ib->ptr[ib->length_dw++] = 0x00000001;
540
676
 	ib->ptr[ib->length_dw++] = handle;
541
-	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
542
-	ib->ptr[ib->length_dw++] = dummy;
677
+	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
678
+	ib->ptr[ib->length_dw++] = addr;
543
679
 	ib->ptr[ib->length_dw++] = 0x0000000b;
544
680
 
545
681
 	ib->ptr[ib->length_dw++] = 0x00000014;
..
..
@@ -572,155 +708,32 @@
572
708
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
573
709
 {
574
710
 	struct dma_fence *fence = NULL;
711
+	struct amdgpu_bo *bo = NULL;
575
712
 	long r;
576
713
 
577
-	r = amdgpu_vcn_enc_get_create_msg(ring, 1, NULL);
578
-	if (r) {
579
-		DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
580
-		goto error;
581
-	}
582
-
583
-	r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &fence);
584
-	if (r) {
585
-		DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
586
-		goto error;
587
-	}
588
-
589
-	r = dma_fence_wait_timeout(fence, false, timeout);
590
-	if (r == 0) {
591
-		DRM_ERROR("amdgpu: IB test timed out.\n");
592
-		r = -ETIMEDOUT;
593
-	} else if (r < 0) {
594
-		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
595
-	} else {
596
-		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
597
-		r = 0;
598
-	}
599
-error:
600
-	dma_fence_put(fence);
601
-	return r;
602
-}
603
-
604
-int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
605
-{
606
-	struct amdgpu_device *adev = ring->adev;
607
-	uint32_t tmp = 0;
608
-	unsigned i;
609
-	int r;
610
-
611
-	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
612
-	r = amdgpu_ring_alloc(ring, 3);
613
-
614
-	if (r) {
615
-		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
616
-				  ring->idx, r);
617
-		return r;
618
-	}
619
-
620
-	amdgpu_ring_write(ring,
621
-		PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
622
-	amdgpu_ring_write(ring, 0xDEADBEEF);
623
-	amdgpu_ring_commit(ring);
624
-
625
-	for (i = 0; i < adev->usec_timeout; i++) {
626
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
627
-		if (tmp == 0xDEADBEEF)
628
-			break;
629
-		DRM_UDELAY(1);
630
-	}
631
-
632
-	if (i < adev->usec_timeout) {
633
-		DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
634
-				  ring->idx, i);
635
-	} else {
636
-		DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
637
-				  ring->idx, tmp);
638
-		r = -EINVAL;
639
-	}
640
-
641
-	return r;
642
-}
643
-
644
-static int amdgpu_vcn_jpeg_set_reg(struct amdgpu_ring *ring, uint32_t handle,
645
-		struct dma_fence **fence)
646
-{
647
-	struct amdgpu_device *adev = ring->adev;
648
-	struct amdgpu_job *job;
649
-	struct amdgpu_ib *ib;
650
-	struct dma_fence *f = NULL;
651
-	const unsigned ib_size_dw = 16;
652
-	int i, r;
653
-
654
-	r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
714
+	r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
715
+				      AMDGPU_GEM_DOMAIN_VRAM,
716
+				      &bo, NULL, NULL);
655
717
 	if (r)
656
718
 		return r;
657
719
 
658
-	ib = &job->ibs[0];
659
-
660
-	ib->ptr[0] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH), 0, 0, PACKETJ_TYPE0);
661
-	ib->ptr[1] = 0xDEADBEEF;
662
-	for (i = 2; i < 16; i += 2) {
663
-		ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
664
-		ib->ptr[i+1] = 0;
665
-	}
666
-	ib->length_dw = 16;
667
-
668
-	r = amdgpu_job_submit_direct(job, ring, &f);
720
+	r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
669
721
 	if (r)
670
-		goto err;
671
-
672
-	if (fence)
673
-		*fence = dma_fence_get(f);
674
-	dma_fence_put(f);
675
-
676
-	return 0;
677
-
678
-err:
679
-	amdgpu_job_free(job);
680
-	return r;
681
-}
682
-
683
-int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout)
684
-{
685
-	struct amdgpu_device *adev = ring->adev;
686
-	uint32_t tmp = 0;
687
-	unsigned i;
688
-	struct dma_fence *fence = NULL;
689
-	long r = 0;
690
-
691
-	r = amdgpu_vcn_jpeg_set_reg(ring, 1, &fence);
692
-	if (r) {
693
-		DRM_ERROR("amdgpu: failed to set jpeg register (%ld).\n", r);
694
722
 		goto error;
695
-	}
723
+
724
+	r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
725
+	if (r)
726
+		goto error;
696
727
 
697
728
 	r = dma_fence_wait_timeout(fence, false, timeout);
698
-	if (r == 0) {
699
-		DRM_ERROR("amdgpu: IB test timed out.\n");
729
+	if (r == 0)
700
730
 		r = -ETIMEDOUT;
701
-		goto error;
702
-	} else if (r < 0) {
703
-		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
704
-		goto error;
705
-	} else
731
+	else if (r > 0)
706
732
 		r = 0;
707
733
 
708
-	for (i = 0; i < adev->usec_timeout; i++) {
709
-		tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH));
710
-		if (tmp == 0xDEADBEEF)
711
-			break;
712
-		DRM_UDELAY(1);
713
-	}
714
-
715
-	if (i < adev->usec_timeout)
716
-		DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
717
-	else {
718
-		DRM_ERROR("ib test failed (0x%08X)\n", tmp);
719
-		r = -EINVAL;
720
-	}
721
-
722
-	dma_fence_put(fence);
723
-
724
734
 error:
735
+	dma_fence_put(fence);
736
+	amdgpu_bo_unreserve(bo);
737
+	amdgpu_bo_unref(&bo);
725
738
 	return r;
726
739
 }