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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
..
..
@@ -24,7 +24,7 @@
24
24
 #include <linux/firmware.h>
25
25
 #include <linux/slab.h>
26
26
 #include <linux/module.h>
27
-#include <drm/drmP.h>
27
+
28
28
 #include "amdgpu.h"
29
29
 #include "amdgpu_ucode.h"
30
30
 
..
..
@@ -77,6 +77,14 @@
77
77
 			container_of(hdr, struct smc_firmware_header_v1_0, header);
78
78
 
79
79
 		DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
80
+	} else if (version_major == 2) {
81
+		const struct smc_firmware_header_v1_0 *v1_hdr =
82
+			container_of(hdr, struct smc_firmware_header_v1_0, header);
83
+		const struct smc_firmware_header_v2_0 *v2_hdr =
84
+			container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
85
+
86
+		DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
87
+		DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
80
88
 	} else {
81
89
 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
82
90
 	}
..
..
@@ -227,6 +235,80 @@
227
235
 	}
228
236
 }
229
237
 
238
+void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
239
+{
240
+	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
241
+	uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
242
+
243
+	DRM_DEBUG("PSP\n");
244
+	amdgpu_ucode_print_common_hdr(hdr);
245
+
246
+	if (version_major == 1) {
247
+		const struct psp_firmware_header_v1_0 *psp_hdr =
248
+			container_of(hdr, struct psp_firmware_header_v1_0, header);
249
+
250
+		DRM_DEBUG("ucode_feature_version: %u\n",
251
+			  le32_to_cpu(psp_hdr->ucode_feature_version));
252
+		DRM_DEBUG("sos_offset_bytes: %u\n",
253
+			  le32_to_cpu(psp_hdr->sos_offset_bytes));
254
+		DRM_DEBUG("sos_size_bytes: %u\n",
255
+			  le32_to_cpu(psp_hdr->sos_size_bytes));
256
+		if (version_minor == 1) {
257
+			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
258
+				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
259
+			DRM_DEBUG("toc_header_version: %u\n",
260
+				  le32_to_cpu(psp_hdr_v1_1->toc_header_version));
261
+			DRM_DEBUG("toc_offset_bytes: %u\n",
262
+				  le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));
263
+			DRM_DEBUG("toc_size_bytes: %u\n",
264
+				  le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));
265
+			DRM_DEBUG("kdb_header_version: %u\n",
266
+				  le32_to_cpu(psp_hdr_v1_1->kdb_header_version));
267
+			DRM_DEBUG("kdb_offset_bytes: %u\n",
268
+				  le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));
269
+			DRM_DEBUG("kdb_size_bytes: %u\n",
270
+				  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
271
+		}
272
+		if (version_minor == 2) {
273
+			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
274
+				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
275
+			DRM_DEBUG("kdb_header_version: %u\n",
276
+				  le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
277
+			DRM_DEBUG("kdb_offset_bytes: %u\n",
278
+				  le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
279
+			DRM_DEBUG("kdb_size_bytes: %u\n",
280
+				  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
281
+		}
282
+		if (version_minor == 3) {
283
+			const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
284
+				container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
285
+			const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
286
+				container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
287
+			DRM_DEBUG("toc_header_version: %u\n",
288
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));
289
+			DRM_DEBUG("toc_offset_bytes: %u\n",
290
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));
291
+			DRM_DEBUG("toc_size_bytes: %u\n",
292
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));
293
+			DRM_DEBUG("kdb_header_version: %u\n",
294
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));
295
+			DRM_DEBUG("kdb_offset_bytes: %u\n",
296
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));
297
+			DRM_DEBUG("kdb_size_bytes: %u\n",
298
+				  le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));
299
+			DRM_DEBUG("spl_header_version: %u\n",
300
+				  le32_to_cpu(psp_hdr_v1_3->spl_header_version));
301
+			DRM_DEBUG("spl_offset_bytes: %u\n",
302
+				  le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));
303
+			DRM_DEBUG("spl_size_bytes: %u\n",
304
+				  le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));
305
+		}
306
+	} else {
307
+		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
308
+			  version_major, version_minor);
309
+	}
310
+}
311
+
230
312
 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
231
313
 {
232
314
 	uint16_t version_major = le16_to_cpu(hdr->header_version_major);
..
..
@@ -297,24 +379,90 @@
297
379
 	case CHIP_POLARIS11:
298
380
 	case CHIP_POLARIS12:
299
381
 	case CHIP_VEGAM:
300
-		if (!load_type)
301
-			return AMDGPU_FW_LOAD_DIRECT;
302
-		else
303
-			return AMDGPU_FW_LOAD_SMU;
382
+		return AMDGPU_FW_LOAD_SMU;
304
383
 	case CHIP_VEGA10:
305
384
 	case CHIP_RAVEN:
306
385
 	case CHIP_VEGA12:
386
+	case CHIP_VEGA20:
387
+	case CHIP_ARCTURUS:
388
+	case CHIP_RENOIR:
389
+	case CHIP_NAVI10:
390
+	case CHIP_NAVI14:
391
+	case CHIP_NAVI12:
392
+	case CHIP_SIENNA_CICHLID:
393
+	case CHIP_NAVY_FLOUNDER:
307
394
 		if (!load_type)
308
395
 			return AMDGPU_FW_LOAD_DIRECT;
309
396
 		else
310
397
 			return AMDGPU_FW_LOAD_PSP;
311
-	case CHIP_VEGA20:
312
-		return AMDGPU_FW_LOAD_DIRECT;
313
398
 	default:
314
399
 		DRM_ERROR("Unknown firmware load type\n");
315
400
 	}
316
401
 
317
402
 	return AMDGPU_FW_LOAD_DIRECT;
403
+}
404
+
405
+#define FW_VERSION_ATTR(name, mode, field)				\
406
+static ssize_t show_##name(struct device *dev,				\
407
+			  struct device_attribute *attr,		\
408
+			  char *buf)					\
409
+{									\
410
+	struct drm_device *ddev = dev_get_drvdata(dev);			\
411
+	struct amdgpu_device *adev = drm_to_adev(ddev);			\
412
+									\
413
+	return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);	\
414
+}									\
415
+static DEVICE_ATTR(name, mode, show_##name, NULL)
416
+
417
+FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
418
+FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
419
+FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
420
+FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
421
+FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
422
+FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
423
+FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
424
+FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
425
+FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
426
+FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
427
+FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
428
+FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
429
+FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version);
430
+FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version);
431
+FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_ras_ucode_version);
432
+FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_xgmi_ucode_version);
433
+FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
434
+FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
435
+FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
436
+FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
437
+FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
438
+
439
+static struct attribute *fw_attrs[] = {
440
+	&dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
441
+	&dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
442
+	&dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
443
+	&dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
444
+	&dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
445
+	&dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
446
+	&dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
447
+	&dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
448
+	&dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
449
+	&dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
450
+	&dev_attr_dmcu_fw_version.attr, NULL
451
+};
452
+
453
+static const struct attribute_group fw_attr_group = {
454
+	.name = "fw_version",
455
+	.attrs = fw_attrs
456
+};
457
+
458
+int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
459
+{
460
+	return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
461
+}
462
+
463
+void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
464
+{
465
+	sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
318
466
 }
319
467
 
320
468
 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
..
..
@@ -323,6 +471,9 @@
323
471
 {
324
472
 	const struct common_firmware_header *header = NULL;
325
473
 	const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
474
+	const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
475
+	const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
476
+	const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
326
477
 
327
478
 	if (NULL == ucode->fw)
328
479
 		return 0;
..
..
@@ -334,17 +485,26 @@
334
485
 		return 0;
335
486
 
336
487
 	header = (const struct common_firmware_header *)ucode->fw->data;
337
-
338
488
 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
489
+	dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
490
+	dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
491
+	mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
339
492
 
340
493
 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
341
494
 	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
342
495
 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
343
496
 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
344
497
 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
498
+	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
499
+	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
345
500
 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
346
501
 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
347
-	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
502
+	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
503
+	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
504
+	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
505
+		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
506
+		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
507
+		 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
348
508
 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
349
509
 
350
510
 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
..
..
@@ -366,6 +526,26 @@
366
526
 					      le32_to_cpu(header->ucode_array_offset_bytes) +
367
527
 					      le32_to_cpu(cp_hdr->jt_offset) * 4),
368
528
 		       ucode->ucode_size);
529
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
530
+		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
531
+				le32_to_cpu(dmcu_hdr->intv_size_bytes);
532
+
533
+		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
534
+					      le32_to_cpu(header->ucode_array_offset_bytes)),
535
+		       ucode->ucode_size);
536
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
537
+		ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
538
+
539
+		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
540
+					      le32_to_cpu(header->ucode_array_offset_bytes) +
541
+					      le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
542
+		       ucode->ucode_size);
543
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
544
+		ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
545
+		memcpy(ucode->kaddr,
546
+		       (void *)((uint8_t *)ucode->fw->data +
547
+				le32_to_cpu(header->ucode_array_offset_bytes)),
548
+		       ucode->ucode_size);
369
549
 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
370
550
 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
371
551
 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
..
..
@@ -377,6 +557,24 @@
377
557
 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
378
558
 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
379
559
 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
560
+		       ucode->ucode_size);
561
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
562
+		ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
563
+		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
564
+		       ucode->ucode_size);
565
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
566
+		ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
567
+		memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
568
+		       ucode->ucode_size);
569
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
570
+		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
571
+		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
572
+			      le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
573
+		       ucode->ucode_size);
574
+	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
575
+		ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
576
+		memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
577
+			      le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
380
578
 		       ucode->ucode_size);
381
579
 	}
382
580
 
..
..
@@ -407,32 +605,40 @@
407
605
 	return 0;
408
606
 }
409
607
 
608
+int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
609
+{
610
+	if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
611
+		amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
612
+			amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
613
+			&adev->firmware.fw_buf,
614
+			&adev->firmware.fw_buf_mc,
615
+			&adev->firmware.fw_buf_ptr);
616
+		if (!adev->firmware.fw_buf) {
617
+			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
618
+			return -ENOMEM;
619
+		} else if (amdgpu_sriov_vf(adev)) {
620
+			memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
621
+		}
622
+	}
623
+	return 0;
624
+}
625
+
626
+void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
627
+{
628
+	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
629
+		&adev->firmware.fw_buf_mc,
630
+		&adev->firmware.fw_buf_ptr);
631
+}
632
+
410
633
 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
411
634
 {
412
635
 	uint64_t fw_offset = 0;
413
-	int i, err;
636
+	int i;
414
637
 	struct amdgpu_firmware_info *ucode = NULL;
415
-	const struct common_firmware_header *header = NULL;
416
638
 
417
-	if (!adev->firmware.fw_size) {
418
-		dev_warn(adev->dev, "No ip firmware need to load\n");
639
+ /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
640
+	if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
419
641
 		return 0;
420
-	}
421
-
422
-	if (!adev->in_gpu_reset) {
423
-		err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
424
-					amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
425
-					&adev->firmware.fw_buf,
426
-					&adev->firmware.fw_buf_mc,
427
-					&adev->firmware.fw_buf_ptr);
428
-		if (err) {
429
-			dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
430
-			goto failed;
431
-		}
432
-	}
433
-
434
-	memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
435
-
436
642
 	/*
437
643
 	 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
438
644
 	 * ucode info here
..
..
@@ -449,7 +655,6 @@
449
655
 	for (i = 0; i < adev->firmware.max_ucodes; i++) {
450
656
 		ucode = &adev->firmware.ucode[i];
451
657
 		if (ucode->fw) {
452
-			header = (const struct common_firmware_header *)ucode->fw->data;
453
658
 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
454
659
 						    adev->firmware.fw_buf_ptr + fw_offset);
455
660
 			if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
..
..
@@ -463,34 +668,5 @@
463
668
 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
464
669
 		}
465
670
 	}
466
-	return 0;
467
-
468
-failed:
469
-	if (err)
470
-		adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
471
-
472
-	return err;
473
-}
474
-
475
-int amdgpu_ucode_fini_bo(struct amdgpu_device *adev)
476
-{
477
-	int i;
478
-	struct amdgpu_firmware_info *ucode = NULL;
479
-
480
-	if (!adev->firmware.fw_size)
481
-		return 0;
482
-
483
-	for (i = 0; i < adev->firmware.max_ucodes; i++) {
484
-		ucode = &adev->firmware.ucode[i];
485
-		if (ucode->fw) {
486
-			ucode->mc_addr = 0;
487
-			ucode->kaddr = NULL;
488
-		}
489
-	}
490
-
491
-	amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
492
-				&adev->firmware.fw_buf_mc,
493
-				&adev->firmware.fw_buf_ptr);
494
-
495
671
 	return 0;
496
672
 }