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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
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@@ -29,11 +29,16 @@
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 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1)
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 /* bit set means context switch occured */
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 #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2)
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+/* bit set means IB is preempted */
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+#define AMDGPU_IB_PREEMPTED                 (1 << 3)
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 #define to_amdgpu_job(sched_job)		\
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 		container_of((sched_job), struct amdgpu_job, base)
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+#define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
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+
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 struct amdgpu_fence;
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+enum amdgpu_ib_pool_type;
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 struct amdgpu_job {
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 	struct drm_sched_job    base;
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@@ -43,8 +48,8 @@
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 	struct amdgpu_ib	*ibs;
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 	struct dma_fence	*fence; /* the hw fence */
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 	uint32_t		preamble_status;
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+	uint32_t                preemption_status;
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 	uint32_t		num_ibs;
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-	void			*owner;
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 	bool                    vm_needs_flush;
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 	uint64_t		vm_pd_addr;
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 	unsigned		vmid;
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@@ -57,18 +62,19 @@
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 	/* user fence handling */
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 	uint64_t		uf_addr;
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 	uint64_t		uf_sequence;
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-
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 };
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 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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 		     struct amdgpu_job **job, struct amdgpu_vm *vm);
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 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
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-			     struct amdgpu_job **job);
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-
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+		enum amdgpu_ib_pool_type pool, struct amdgpu_job **job);
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 void amdgpu_job_free_resources(struct amdgpu_job *job);
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 void amdgpu_job_free(struct amdgpu_job *job);
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 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
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 		      void *owner, struct dma_fence **f);
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 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
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 			     struct dma_fence **fence);
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+
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+void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched);
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+
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 #endif