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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
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@@ -24,7 +24,7 @@
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 #include <linux/kthread.h>
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 #include <linux/wait.h>
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 #include <linux/sched.h>
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-#include <drm/drmP.h>
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+
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 #include "amdgpu.h"
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 #include "amdgpu_trace.h"
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30
 
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@@ -32,12 +32,32 @@
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 {
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 	struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
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 	struct amdgpu_job *job = to_amdgpu_job(s_job);
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+	struct amdgpu_task_info ti;
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+	struct amdgpu_device *adev = ring->adev;
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37
 
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+	memset(&ti, 0, sizeof(struct amdgpu_task_info));
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+
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+	if (amdgpu_gpu_recovery &&
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+	    amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
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+		DRM_ERROR("ring %s timeout, but soft recovered\n",
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+			  s_job->sched->name);
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+		return;
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+	}
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+
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+	amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
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 	DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
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 		  job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
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 		  ring->fence_drv.sync_seq);
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+	DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
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+		  ti.process_name, ti.tgid, ti.task_name, ti.pid);
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53
 
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-	amdgpu_device_gpu_recover(ring->adev, job, false);
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+	if (amdgpu_device_should_recover_gpu(ring->adev)) {
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+		amdgpu_device_gpu_recover(ring->adev, job);
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+	} else {
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+		drm_sched_suspend_timeout(&ring->sched);
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+		if (amdgpu_sriov_vf(adev))
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+			adev->virt.tdr_debug = true;
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+	}
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 }
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62
 
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 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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@@ -72,7 +92,8 @@
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 }
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93
 
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 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
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-			     struct amdgpu_job **job)
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+		enum amdgpu_ib_pool_type pool_type,
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+		struct amdgpu_job **job)
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 {
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 	int r;
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99
 
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@@ -80,11 +101,9 @@
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 	if (r)
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 		return r;
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-	r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
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+	r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
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 	if (r)
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 		kfree(*job);
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-	else
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-		(*job)->vm_pd_addr = adev->gart.table_addr;
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107
 
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 	return r;
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 }
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@@ -104,10 +123,10 @@
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123
 
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 static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
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 {
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-	struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
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 	struct amdgpu_job *job = to_amdgpu_job(s_job);
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127
 
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-	amdgpu_ring_priority_put(ring, s_job->s_priority);
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+	drm_sched_job_cleanup(s_job);
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+
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 	dma_fence_put(job->fence);
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 	amdgpu_sync_free(&job->sync);
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 	amdgpu_sync_free(&job->sched_sync);
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@@ -127,8 +146,6 @@
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 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
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 		      void *owner, struct dma_fence **f)
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 {
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-	enum drm_sched_priority priority;
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-	struct amdgpu_ring *ring;
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 	int r;
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150
 
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 	if (!f)
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@@ -138,14 +155,9 @@
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 	if (r)
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 		return r;
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-	job->owner = owner;
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 	*f = dma_fence_get(&job->base.s_fence->finished);
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 	amdgpu_job_free_resources(job);
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-	priority = job->base.s_priority;
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 	drm_sched_entity_push_job(&job->base, entity);
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-
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-	ring = to_amdgpu_ring(entity->rq->sched);
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-	amdgpu_ring_priority_get(ring, priority);
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161
 
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 	return 0;
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 }
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@@ -172,17 +184,13 @@
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 	struct amdgpu_job *job = to_amdgpu_job(sched_job);
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 	struct amdgpu_vm *vm = job->vm;
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 	struct dma_fence *fence;
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-	bool explicit = false;
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 	int r;
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188
 
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-	fence = amdgpu_sync_get_fence(&job->sync, &explicit);
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-	if (fence && explicit) {
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-		if (drm_sched_dependency_optimized(fence, s_entity)) {
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-			r = amdgpu_sync_fence(ring->adev, &job->sched_sync,
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-					      fence, false);
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-			if (r)
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-				DRM_ERROR("Error adding fence (%d)\n", r);
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-		}
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+	fence = amdgpu_sync_get_fence(&job->sync);
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+	if (fence && drm_sched_dependency_optimized(fence, s_entity)) {
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+		r = amdgpu_sync_fence(&job->sched_sync, fence);
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+		if (r)
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+			DRM_ERROR("Error adding fence (%d)\n", r);
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 	}
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195
 
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 	while (fence == NULL && vm && !job->vmid) {
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@@ -192,7 +200,7 @@
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 		if (r)
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 			DRM_ERROR("Error getting VM ID (%d)\n", r);
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-		fence = amdgpu_sync_get_fence(&job->sync, NULL);
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+		fence = amdgpu_sync_get_fence(&job->sync);
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 	}
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 	return fence;
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@@ -233,6 +241,44 @@
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 	return fence;
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 }
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243
 
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+#define to_drm_sched_job(sched_job)		\
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+		container_of((sched_job), struct drm_sched_job, queue_node)
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+
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+void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
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+{
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+	struct drm_sched_job *s_job;
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+	struct drm_sched_entity *s_entity = NULL;
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+	int i;
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+
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+	/* Signal all jobs not yet scheduled */
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+	for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
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+		struct drm_sched_rq *rq = &sched->sched_rq[i];
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+
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+		if (!rq)
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+			continue;
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+
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+		spin_lock(&rq->lock);
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+		list_for_each_entry(s_entity, &rq->entities, list) {
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+			while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
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+				struct drm_sched_fence *s_fence = s_job->s_fence;
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+
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+				dma_fence_signal(&s_fence->scheduled);
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+				dma_fence_set_error(&s_fence->finished, -EHWPOISON);
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+				dma_fence_signal(&s_fence->finished);
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+			}
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+		}
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+		spin_unlock(&rq->lock);
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+	}
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+
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+	/* Signal all jobs already scheduled to HW */
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+	list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
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+		struct drm_sched_fence *s_fence = s_job->s_fence;
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+
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+		dma_fence_set_error(&s_fence->finished, -EHWPOISON);
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+		dma_fence_signal(&s_fence->finished);
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+	}
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+}
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+
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 const struct drm_sched_backend_ops amdgpu_sched_ops = {
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 	.dependency = amdgpu_job_dependency,
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 	.run_job = amdgpu_job_run,