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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c
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@@ -1,7 +1,7 @@
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 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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 /*
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  *
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- * (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
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+ * (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
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  *
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  * This program is free software and is provided to you under the terms of the
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  * GNU General Public License version 2 as published by the Free Software
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@@ -24,6 +24,7 @@
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 #include <backend/gpu/mali_kbase_instr_internal.h>
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 #include <backend/gpu/mali_kbase_pm_internal.h>
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 #include <device/mali_kbase_device.h>
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+#include <device/mali_kbase_device_internal.h>
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 #include <mali_kbase_reset_gpu.h>
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 #include <mmu/mali_kbase_mmu.h>
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 #include <mali_kbase_ctx_sched.h>
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@@ -80,6 +81,7 @@
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 		}
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 	} else
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 		kbase_report_gpu_fault(kbdev, status, as_nr, as_valid);
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+
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 }
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 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
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@@ -114,6 +116,9 @@
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 									GPU_EXCEPTION_TYPE_SW_FAULT_0,
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 							} } };
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+			kbase_debug_csf_fault_notify(kbdev, scheduler->active_protm_grp->kctx,
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+						     DF_GPU_PROTECTED_FAULT);
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+
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 			scheduler->active_protm_grp->faulted = true;
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 			kbase_csf_add_group_fatal_error(
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 				scheduler->active_protm_grp, &err_payload);
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@@ -124,13 +129,33 @@
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 		if (kbase_prepare_to_reset_gpu(
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 			    kbdev, RESET_FLAGS_HWC_UNRECOVERABLE_ERROR))
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 			kbase_reset_gpu(kbdev);
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+
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+		/* Defer the clearing to the GPU reset sequence */
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+		val &= ~GPU_PROTECTED_FAULT;
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 	}
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 	if (val & RESET_COMPLETED)
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 		kbase_pm_reset_done(kbdev);
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-	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val);
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-	kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val);
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+	/* Defer clearing CLEAN_CACHES_COMPLETED to kbase_clean_caches_done.
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+	 * We need to acquire hwaccess_lock to avoid a race condition with
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+	 * kbase_gpu_cache_flush_and_busy_wait
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+	 */
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+	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val & ~CLEAN_CACHES_COMPLETED);
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+	kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED);
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+
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+#ifdef KBASE_PM_RUNTIME
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+	if (val & DOORBELL_MIRROR) {
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+		unsigned long flags;
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+
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+		dev_dbg(kbdev->dev, "Doorbell mirror interrupt received");
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+		spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
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+		kbase_pm_disable_db_mirror_interrupt(kbdev);
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+		kbdev->pm.backend.exit_gpu_sleep_mode = true;
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+		kbase_csf_scheduler_invoke_tick(kbdev);
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+		spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
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+	}
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+#endif
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 	/* kbase_pm_check_transitions (called by kbase_pm_power_changed) must
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 	 * be called after the IRQ has been cleared. This is because it might
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@@ -160,3 +185,68 @@
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 	KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
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 }
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+
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+#if !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
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+bool kbase_is_register_accessible(u32 offset)
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+{
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+#ifdef CONFIG_MALI_BIFROST_DEBUG
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+	if (((offset >= MCU_SUBSYSTEM_BASE) && (offset < IPA_CONTROL_BASE)) ||
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+	    ((offset >= GPU_CONTROL_MCU_BASE) && (offset < USER_BASE))) {
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+		WARN(1, "Invalid register offset 0x%x", offset);
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+		return false;
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+	}
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+#endif
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+
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+	return true;
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+}
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+#endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
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+
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+#if IS_ENABLED(CONFIG_MALI_REAL_HW)
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+void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
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+{
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+	if (WARN_ON(!kbdev->pm.backend.gpu_powered))
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+		return;
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+
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+	if (WARN_ON(kbdev->dev == NULL))
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+		return;
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+
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+	if (!kbase_is_register_accessible(offset))
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+		return;
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+
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+	writel(value, kbdev->reg + offset);
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+
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+#if IS_ENABLED(CONFIG_DEBUG_FS)
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+	if (unlikely(kbdev->io_history.enabled))
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+		kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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+				     value, 1);
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+#endif /* CONFIG_DEBUG_FS */
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+	dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
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+}
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+KBASE_EXPORT_TEST_API(kbase_reg_write);
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+
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+u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
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+{
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+	u32 val;
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+
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+	if (WARN_ON(!kbdev->pm.backend.gpu_powered))
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+		return 0;
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+
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+	if (WARN_ON(kbdev->dev == NULL))
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+		return 0;
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+
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+	if (!kbase_is_register_accessible(offset))
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+		return 0;
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+
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+	val = readl(kbdev->reg + offset);
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+
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+#if IS_ENABLED(CONFIG_DEBUG_FS)
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+	if (unlikely(kbdev->io_history.enabled))
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+		kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
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+				     val, 0);
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+#endif /* CONFIG_DEBUG_FS */
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+	dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
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+
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+	return val;
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+}
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+KBASE_EXPORT_TEST_API(kbase_reg_read);
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+#endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */