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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/cpufreq/tegra124-cpufreq.c
..
..
@@ -1,19 +1,12 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * Tegra 124 cpufreq driver
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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4
  */
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5
 
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 #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
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7
 
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 #include <linux/clk.h>
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+#include <linux/cpufreq.h>
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10
 #include <linux/err.h>
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11
 #include <linux/init.h>
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12
 #include <linux/kernel.h>
..
..
@@ -22,11 +15,9 @@
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 #include <linux/of.h>
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16
 #include <linux/platform_device.h>
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17
 #include <linux/pm_opp.h>
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-#include <linux/regulator/consumer.h>
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18
 #include <linux/types.h>
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19
 
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 struct tegra124_cpufreq_priv {
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-	struct regulator *vdd_cpu_reg;
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21
 	struct clk *cpu_clk;
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22
 	struct clk *pllp_clk;
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23
 	struct clk *pllx_clk;
..
..
@@ -60,14 +51,6 @@
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 	return ret;
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52
 }
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53
 
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-static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
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-{
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-	clk_set_parent(priv->cpu_clk, priv->pllp_clk);
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-	clk_disable_unprepare(priv->dfll_clk);
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-	regulator_sync_voltage(priv->vdd_cpu_reg);
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-	clk_set_parent(priv->cpu_clk, priv->pllx_clk);
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-}
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-
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54
 static int tegra124_cpufreq_probe(struct platform_device *pdev)
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55
 {
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56
 	struct tegra124_cpufreq_priv *priv;
..
..
@@ -88,16 +71,10 @@
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71
 	if (!np)
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72
 		return -ENODEV;
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73
 
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-	priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
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-	if (IS_ERR(priv->vdd_cpu_reg)) {
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-		ret = PTR_ERR(priv->vdd_cpu_reg);
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-		goto out_put_np;
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-	}
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-
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74
 	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
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75
 	if (IS_ERR(priv->cpu_clk)) {
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 		ret = PTR_ERR(priv->cpu_clk);
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-		goto out_put_vdd_cpu_reg;
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+		goto out_put_np;
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78
 	}
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79
 
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 	priv->dfll_clk = of_clk_get_by_name(np, "dfll");
..
..
@@ -129,7 +106,7 @@
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106
 		platform_device_register_full(&cpufreq_dt_devinfo);
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107
 	if (IS_ERR(priv->cpufreq_dt_pdev)) {
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108
 		ret = PTR_ERR(priv->cpufreq_dt_pdev);
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-		goto out_switch_to_pllx;
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+		goto out_put_pllp_clk;
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110
 	}
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111
 
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 	platform_set_drvdata(pdev, priv);
..
..
@@ -138,8 +115,6 @@
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115
 
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 	return 0;
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117
 
141
-out_switch_to_pllx:
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-	tegra124_cpu_switch_to_pllx(priv);
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118
 out_put_pllp_clk:
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119
 	clk_put(priv->pllp_clk);
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120
 out_put_pllx_clk:
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..
@@ -148,34 +123,73 @@
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123
 	clk_put(priv->dfll_clk);
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124
 out_put_cpu_clk:
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125
 	clk_put(priv->cpu_clk);
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-out_put_vdd_cpu_reg:
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-	regulator_put(priv->vdd_cpu_reg);
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126
 out_put_np:
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127
 	of_node_put(np);
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128
 
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 	return ret;
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130
 }
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131
 
159
-static int tegra124_cpufreq_remove(struct platform_device *pdev)
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+static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
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 {
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-	struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
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+	struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
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+	int err;
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136
 
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-	platform_device_unregister(priv->cpufreq_dt_pdev);
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-	tegra124_cpu_switch_to_pllx(priv);
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+	/*
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+	 * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
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+	 * use during suspend and resume. So, switch the CPU clock source
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+	 * to PLLP and disable DFLL.
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+	 */
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+	err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
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+	if (err < 0) {
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+		dev_err(dev, "failed to reparent to PLLP: %d\n", err);
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+		return err;
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+	}
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147
 
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-	clk_put(priv->pllp_clk);
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-	clk_put(priv->pllx_clk);
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-	clk_put(priv->dfll_clk);
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-	clk_put(priv->cpu_clk);
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-	regulator_put(priv->vdd_cpu_reg);
148
+	clk_disable_unprepare(priv->dfll_clk);
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149
 
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 	return 0;
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151
 }
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152
 
153
+static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
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+{
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+	struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
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+	int err;
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+
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+	/*
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+	 * Warmboot code powers up the CPU with PLLP clock source.
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+	 * Enable DFLL clock and switch CPU clock source back to DFLL.
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+	 */
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+	err = clk_prepare_enable(priv->dfll_clk);
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+	if (err < 0) {
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+		dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
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+		goto disable_cpufreq;
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+	}
167
+
168
+	err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
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+	if (err < 0) {
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+		dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
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+		goto disable_dfll;
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+	}
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+
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+	return 0;
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+
176
+disable_dfll:
177
+	clk_disable_unprepare(priv->dfll_clk);
178
+disable_cpufreq:
179
+	disable_cpufreq();
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+
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+	return err;
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+}
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+
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+static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
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+	SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
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+				tegra124_cpufreq_resume)
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+};
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+
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189
 static struct platform_driver tegra124_cpufreq_platdrv = {
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190
 	.driver.name	= "cpufreq-tegra124",
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+	.driver.pm	= &tegra124_cpufreq_pm_ops,
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192
 	.probe		= tegra124_cpufreq_probe,
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-	.remove		= tegra124_cpufreq_remove,
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193
 };
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194
 
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 static int __init tegra_cpufreq_init(void)
..
..
@@ -183,7 +197,8 @@
183
197
 	int ret;
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198
 	struct platform_device *pdev;
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199
 
186
-	if (!of_machine_is_compatible("nvidia,tegra124"))
200
+	if (!(of_machine_is_compatible("nvidia,tegra124") ||
201
+		of_machine_is_compatible("nvidia,tegra210")))
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202
 		return -ENODEV;
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203
 
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 	/*