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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/cpufreq/s3c2440-cpufreq.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2006-2009 Simtec Electronics
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  *	http://armlinux.simtec.co.uk/
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@@ -5,10 +6,6 @@
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  *	Vincent Sanders <vince@simtec.co.uk>
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  *
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  * S3C2440/S3C2442 CPU Frequency scaling
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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 */
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 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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@@ -23,14 +20,27 @@
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 #include <linux/clk.h>
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 #include <linux/err.h>
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 #include <linux/io.h>
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+#include <linux/soc/samsung/s3c-cpufreq-core.h>
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+#include <linux/soc/samsung/s3c-pm.h>
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 #include <asm/mach/arch.h>
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 #include <asm/mach/map.h>
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-#include <mach/regs-clock.h>
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+#define S3C2440_CLKDIVN_PDIVN	     (1<<0)
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+#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
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+#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
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+#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
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+#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
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+#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
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+#define S3C2440_CLKDIVN_UCLK         (1<<3)
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-#include <plat/cpu.h>
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-#include <plat/cpu-freq-core.h>
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+#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
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+#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
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+#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
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+#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
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+#define S3C2440_CAMDIVN_DVSEN        (1<<12)
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+
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+#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
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 static struct clk *xtal;
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 static struct clk *fclk;
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@@ -146,8 +156,8 @@
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 	s3c_freq_dbg("%s: divisors: h=%d, p=%d\n", __func__,
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 		     cfg->divs.h_divisor, cfg->divs.p_divisor);
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-	clkdiv = __raw_readl(S3C2410_CLKDIVN);
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-	camdiv = __raw_readl(S3C2440_CAMDIVN);
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+	clkdiv = s3c24xx_read_clkdivn();
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+	camdiv = s3c2440_read_camdivn();
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 	clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
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 	camdiv &= ~CAMDIVN_HCLK_HALF;
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@@ -187,11 +197,11 @@
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 	 * then make a short delay and remove the hclk halving if necessary.
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 	 */
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-	__raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
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-	__raw_writel(clkdiv, S3C2410_CLKDIVN);
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+	s3c2440_write_camdivn(camdiv | CAMDIVN_HCLK_HALF);
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+	s3c24xx_write_clkdivn(clkdiv);
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 	ndelay(20);
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-	__raw_writel(camdiv, S3C2440_CAMDIVN);
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+	s3c2440_write_camdivn(camdiv);
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 	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
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 }