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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * NVDIMM Firmware Interface Table - NFIT |
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3 | 4 | * |
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4 | 5 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of version 2 of the GNU General Public License as |
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8 | | - * published by the Free Software Foundation. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, but |
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11 | | - * WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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13 | | - * General Public License for more details. |
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14 | 6 | */ |
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15 | 7 | #ifndef __NFIT_H__ |
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16 | 8 | #define __NFIT_H__ |
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.. | .. |
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24 | 16 | /* ACPI 6.1 */ |
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25 | 17 | #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba" |
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26 | 18 | |
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27 | | -/* http://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */ |
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| 19 | +/* https://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */ |
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28 | 20 | #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66" |
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| 21 | +#define UUID_INTEL_BUS "c7d8acd4-2df8-4b82-9f65-a325335af149" |
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29 | 22 | |
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30 | 23 | /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */ |
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31 | 24 | #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6" |
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.. | .. |
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41 | 34 | | ACPI_NFIT_MEM_RESTORE_FAILED | ACPI_NFIT_MEM_FLUSH_FAILED \ |
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42 | 35 | | ACPI_NFIT_MEM_NOT_ARMED | ACPI_NFIT_MEM_MAP_FAILED) |
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43 | 36 | |
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44 | | -#define NVDIMM_FAMILY_MAX NVDIMM_FAMILY_HYPERV |
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| 37 | +#define NVDIMM_CMD_MAX 31 |
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45 | 38 | |
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46 | 39 | #define NVDIMM_STANDARD_CMDMASK \ |
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47 | 40 | (1 << ND_CMD_SMART | 1 << ND_CMD_SMART_THRESHOLD | 1 << ND_CMD_DIMM_FLAGS \ |
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.. | .. |
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63 | 56 | NVDIMM_INTEL_QUERY_FWUPDATE = 16, |
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64 | 57 | NVDIMM_INTEL_SET_THRESHOLD = 17, |
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65 | 58 | NVDIMM_INTEL_INJECT_ERROR = 18, |
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| 59 | + NVDIMM_INTEL_GET_SECURITY_STATE = 19, |
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| 60 | + NVDIMM_INTEL_SET_PASSPHRASE = 20, |
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| 61 | + NVDIMM_INTEL_DISABLE_PASSPHRASE = 21, |
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| 62 | + NVDIMM_INTEL_UNLOCK_UNIT = 22, |
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| 63 | + NVDIMM_INTEL_FREEZE_LOCK = 23, |
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| 64 | + NVDIMM_INTEL_SECURE_ERASE = 24, |
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| 65 | + NVDIMM_INTEL_OVERWRITE = 25, |
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| 66 | + NVDIMM_INTEL_QUERY_OVERWRITE = 26, |
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| 67 | + NVDIMM_INTEL_SET_MASTER_PASSPHRASE = 27, |
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| 68 | + NVDIMM_INTEL_MASTER_SECURE_ERASE = 28, |
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| 69 | + NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO = 29, |
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| 70 | + NVDIMM_INTEL_FW_ACTIVATE_ARM = 30, |
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66 | 71 | }; |
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| 72 | + |
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| 73 | +enum nvdimm_bus_family_cmds { |
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| 74 | + NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO = 1, |
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| 75 | + NVDIMM_BUS_INTEL_FW_ACTIVATE = 2, |
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| 76 | +}; |
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| 77 | + |
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| 78 | +#define NVDIMM_INTEL_SECURITY_CMDMASK \ |
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| 79 | +(1 << NVDIMM_INTEL_GET_SECURITY_STATE | 1 << NVDIMM_INTEL_SET_PASSPHRASE \ |
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| 80 | +| 1 << NVDIMM_INTEL_DISABLE_PASSPHRASE | 1 << NVDIMM_INTEL_UNLOCK_UNIT \ |
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| 81 | +| 1 << NVDIMM_INTEL_FREEZE_LOCK | 1 << NVDIMM_INTEL_SECURE_ERASE \ |
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| 82 | +| 1 << NVDIMM_INTEL_OVERWRITE | 1 << NVDIMM_INTEL_QUERY_OVERWRITE \ |
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| 83 | +| 1 << NVDIMM_INTEL_SET_MASTER_PASSPHRASE \ |
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| 84 | +| 1 << NVDIMM_INTEL_MASTER_SECURE_ERASE) |
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| 85 | + |
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| 86 | +#define NVDIMM_INTEL_FW_ACTIVATE_CMDMASK \ |
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| 87 | +(1 << NVDIMM_INTEL_FW_ACTIVATE_DIMMINFO | 1 << NVDIMM_INTEL_FW_ACTIVATE_ARM) |
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| 88 | + |
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| 89 | +#define NVDIMM_BUS_INTEL_FW_ACTIVATE_CMDMASK \ |
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| 90 | +(1 << NVDIMM_BUS_INTEL_FW_ACTIVATE_BUSINFO | 1 << NVDIMM_BUS_INTEL_FW_ACTIVATE) |
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67 | 91 | |
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68 | 92 | #define NVDIMM_INTEL_CMDMASK \ |
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69 | 93 | (NVDIMM_STANDARD_CMDMASK | 1 << NVDIMM_INTEL_GET_MODES \ |
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70 | 94 | | 1 << NVDIMM_INTEL_GET_FWINFO | 1 << NVDIMM_INTEL_START_FWUPDATE \ |
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71 | 95 | | 1 << NVDIMM_INTEL_SEND_FWUPDATE | 1 << NVDIMM_INTEL_FINISH_FWUPDATE \ |
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72 | 96 | | 1 << NVDIMM_INTEL_QUERY_FWUPDATE | 1 << NVDIMM_INTEL_SET_THRESHOLD \ |
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73 | | - | 1 << NVDIMM_INTEL_INJECT_ERROR | 1 << NVDIMM_INTEL_LATCH_SHUTDOWN) |
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| 97 | + | 1 << NVDIMM_INTEL_INJECT_ERROR | 1 << NVDIMM_INTEL_LATCH_SHUTDOWN \ |
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| 98 | + | NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK) |
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| 99 | + |
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| 100 | +#define NVDIMM_INTEL_DENY_CMDMASK \ |
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| 101 | +(NVDIMM_INTEL_SECURITY_CMDMASK | NVDIMM_INTEL_FW_ACTIVATE_CMDMASK) |
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74 | 102 | |
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75 | 103 | enum nfit_uuids { |
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76 | 104 | /* for simplicity alias the uuid index with the family id */ |
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.. | .. |
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79 | 107 | NFIT_DEV_DIMM_N_HPE2 = NVDIMM_FAMILY_HPE2, |
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80 | 108 | NFIT_DEV_DIMM_N_MSFT = NVDIMM_FAMILY_MSFT, |
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81 | 109 | NFIT_DEV_DIMM_N_HYPERV = NVDIMM_FAMILY_HYPERV, |
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| 110 | + /* |
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| 111 | + * to_nfit_bus_uuid() expects to translate bus uuid family ids |
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| 112 | + * to a UUID index using NVDIMM_FAMILY_MAX as an offset |
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| 113 | + */ |
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| 114 | + NFIT_BUS_INTEL = NVDIMM_FAMILY_MAX + NVDIMM_BUS_FAMILY_INTEL, |
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82 | 115 | NFIT_SPA_VOLATILE, |
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83 | 116 | NFIT_SPA_PM, |
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84 | 117 | NFIT_SPA_DCR, |
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.. | .. |
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133 | 166 | unsigned long ars_state; |
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134 | 167 | u32 clear_err_unit; |
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135 | 168 | u32 max_ars; |
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136 | | - struct acpi_nfit_system_address spa[0]; |
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| 169 | + struct acpi_nfit_system_address spa[]; |
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137 | 170 | }; |
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138 | 171 | |
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139 | 172 | struct nfit_dcr { |
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140 | 173 | struct list_head list; |
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141 | | - struct acpi_nfit_control_region dcr[0]; |
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| 174 | + struct acpi_nfit_control_region dcr[]; |
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142 | 175 | }; |
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143 | 176 | |
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144 | 177 | struct nfit_bdw { |
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145 | 178 | struct list_head list; |
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146 | | - struct acpi_nfit_data_region bdw[0]; |
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| 179 | + struct acpi_nfit_data_region bdw[]; |
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147 | 180 | }; |
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148 | 181 | |
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149 | 182 | struct nfit_idt { |
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150 | 183 | struct list_head list; |
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151 | | - struct acpi_nfit_interleave idt[0]; |
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| 184 | + struct acpi_nfit_interleave idt[]; |
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152 | 185 | }; |
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153 | 186 | |
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154 | 187 | struct nfit_flush { |
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155 | 188 | struct list_head list; |
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156 | | - struct acpi_nfit_flush_address flush[0]; |
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| 189 | + struct acpi_nfit_flush_address flush[]; |
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157 | 190 | }; |
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158 | 191 | |
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159 | 192 | struct nfit_memdev { |
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160 | 193 | struct list_head list; |
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161 | | - struct acpi_nfit_memory_map memdev[0]; |
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| 194 | + struct acpi_nfit_memory_map memdev[]; |
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162 | 195 | }; |
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| 196 | + |
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| 197 | +enum nfit_mem_flags { |
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| 198 | + NFIT_MEM_LSR, |
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| 199 | + NFIT_MEM_LSW, |
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| 200 | + NFIT_MEM_DIRTY, |
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| 201 | + NFIT_MEM_DIRTY_COUNT, |
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| 202 | +}; |
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| 203 | + |
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| 204 | +#define NFIT_DIMM_ID_LEN 22 |
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163 | 205 | |
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164 | 206 | /* assembled tables for a given dimm/memory-device */ |
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165 | 207 | struct nfit_mem { |
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.. | .. |
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178 | 220 | struct list_head list; |
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179 | 221 | struct acpi_device *adev; |
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180 | 222 | struct acpi_nfit_desc *acpi_desc; |
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| 223 | + enum nvdimm_fwa_state fwa_state; |
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| 224 | + enum nvdimm_fwa_result fwa_result; |
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| 225 | + int fwa_count; |
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| 226 | + char id[NFIT_DIMM_ID_LEN+1]; |
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181 | 227 | struct resource *flush_wpq; |
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182 | 228 | unsigned long dsm_mask; |
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| 229 | + unsigned long flags; |
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| 230 | + u32 dirty_shutdown; |
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183 | 231 | int family; |
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184 | | - bool has_lsr; |
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185 | | - bool has_lsw; |
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186 | 232 | }; |
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187 | 233 | |
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188 | 234 | enum scrub_flags { |
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.. | .. |
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216 | 262 | unsigned long scrub_flags; |
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217 | 263 | unsigned long dimm_cmd_force_en; |
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218 | 264 | unsigned long bus_cmd_force_en; |
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219 | | - unsigned long bus_nfit_cmd_force_en; |
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| 265 | + unsigned long bus_dsm_mask; |
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| 266 | + unsigned long family_dsm_mask[NVDIMM_BUS_FAMILY_MAX + 1]; |
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220 | 267 | unsigned int platform_cap; |
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221 | 268 | unsigned int scrub_tmo; |
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222 | 269 | int (*blk_do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
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223 | 270 | void *iobuf, u64 len, int rw); |
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| 271 | + enum nvdimm_fwa_state fwa_state; |
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| 272 | + enum nvdimm_fwa_capability fwa_cap; |
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| 273 | + int fwa_count; |
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| 274 | + bool fwa_noidle; |
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| 275 | + bool fwa_nosuspend; |
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224 | 276 | }; |
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225 | 277 | |
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226 | 278 | enum scrub_mode { |
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.. | .. |
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291 | 343 | return container_of(nd_desc, struct acpi_nfit_desc, nd_desc); |
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292 | 344 | } |
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293 | 345 | |
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| 346 | +#ifdef CONFIG_PROVE_LOCKING |
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| 347 | +static inline void nfit_device_lock(struct device *dev) |
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| 348 | +{ |
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| 349 | + device_lock(dev); |
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| 350 | + mutex_lock(&dev->lockdep_mutex); |
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| 351 | +} |
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| 352 | + |
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| 353 | +static inline void nfit_device_unlock(struct device *dev) |
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| 354 | +{ |
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| 355 | + mutex_unlock(&dev->lockdep_mutex); |
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| 356 | + device_unlock(dev); |
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| 357 | +} |
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| 358 | +#else |
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| 359 | +static inline void nfit_device_lock(struct device *dev) |
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| 360 | +{ |
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| 361 | + device_lock(dev); |
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| 362 | +} |
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| 363 | + |
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| 364 | +static inline void nfit_device_unlock(struct device *dev) |
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| 365 | +{ |
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| 366 | + device_unlock(dev); |
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| 367 | +} |
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| 368 | +#endif |
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| 369 | + |
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294 | 370 | const guid_t *to_nfit_uuid(enum nfit_uuids id); |
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295 | 371 | int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz); |
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296 | 372 | void acpi_nfit_shutdown(void *data); |
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.. | .. |
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299 | 375 | int acpi_nfit_ctl(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm, |
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300 | 376 | unsigned int cmd, void *buf, unsigned int buf_len, int *cmd_rc); |
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301 | 377 | void acpi_nfit_desc_init(struct acpi_nfit_desc *acpi_desc, struct device *dev); |
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| 378 | +bool intel_fwa_supported(struct nvdimm_bus *nvdimm_bus); |
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| 379 | +extern struct device_attribute dev_attr_firmware_activate_noidle; |
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302 | 380 | #endif /* __NFIT_H__ */ |
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