.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * arch/xtensa/kernel/pci.c |
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3 | 4 | * |
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4 | 5 | * PCI bios-type initialisation for PCI machines |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify it |
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7 | | - * under the terms of the GNU General Public License as published by the |
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8 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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9 | | - * option) any later version. |
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10 | 6 | * |
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11 | 7 | * Copyright (C) 2001-2005 Tensilica Inc. |
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12 | 8 | * |
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.. | .. |
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14 | 10 | * IO functions copied from sparc. |
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15 | 11 | * |
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16 | 12 | * Chris Zankel <chris@zankel.net> |
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17 | | - * |
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18 | 13 | */ |
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19 | 14 | |
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20 | 15 | #include <linux/kernel.h> |
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.. | .. |
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24 | 19 | #include <linux/init.h> |
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25 | 20 | #include <linux/sched.h> |
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26 | 21 | #include <linux/errno.h> |
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27 | | -#include <linux/bootmem.h> |
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| 22 | +#include <linux/memblock.h> |
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28 | 23 | |
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29 | 24 | #include <asm/pci-bridge.h> |
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30 | 25 | #include <asm/platform.h> |
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31 | | - |
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32 | | -/* PCI Controller */ |
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33 | | - |
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34 | | - |
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35 | | -/* |
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36 | | - * pcibios_alloc_controller |
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37 | | - * pcibios_enable_device |
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38 | | - * pcibios_fixups |
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39 | | - * pcibios_align_resource |
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40 | | - * pcibios_fixup_bus |
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41 | | - * pci_bus_add_device |
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42 | | - */ |
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43 | | - |
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44 | | -static struct pci_controller *pci_ctrl_head; |
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45 | | -static struct pci_controller **pci_ctrl_tail = &pci_ctrl_head; |
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46 | | - |
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47 | | -static int pci_bus_count; |
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48 | 26 | |
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49 | 27 | /* |
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50 | 28 | * We need to avoid collisions with `mirrored' VGA ports |
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.. | .. |
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80 | 58 | return start; |
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81 | 59 | } |
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82 | 60 | |
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83 | | -static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, |
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84 | | - struct list_head *resources) |
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85 | | -{ |
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86 | | - struct resource *res; |
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87 | | - unsigned long io_offset; |
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88 | | - int i; |
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89 | | - |
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90 | | - io_offset = (unsigned long)pci_ctrl->io_space.base; |
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91 | | - res = &pci_ctrl->io_resource; |
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92 | | - if (!res->flags) { |
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93 | | - if (io_offset) |
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94 | | - pr_err("I/O resource not set for host bridge %d\n", |
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95 | | - pci_ctrl->index); |
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96 | | - res->start = 0; |
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97 | | - res->end = IO_SPACE_LIMIT; |
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98 | | - res->flags = IORESOURCE_IO; |
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99 | | - } |
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100 | | - res->start += io_offset; |
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101 | | - res->end += io_offset; |
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102 | | - pci_add_resource_offset(resources, res, io_offset); |
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103 | | - |
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104 | | - for (i = 0; i < 3; i++) { |
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105 | | - res = &pci_ctrl->mem_resources[i]; |
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106 | | - if (!res->flags) { |
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107 | | - if (i > 0) |
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108 | | - continue; |
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109 | | - pr_err("Memory resource not set for host bridge %d\n", |
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110 | | - pci_ctrl->index); |
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111 | | - res->start = 0; |
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112 | | - res->end = ~0U; |
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113 | | - res->flags = IORESOURCE_MEM; |
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114 | | - } |
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115 | | - pci_add_resource(resources, res); |
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116 | | - } |
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117 | | -} |
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118 | | - |
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119 | | -static int __init pcibios_init(void) |
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120 | | -{ |
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121 | | - struct pci_controller *pci_ctrl; |
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122 | | - struct list_head resources; |
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123 | | - struct pci_bus *bus; |
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124 | | - int next_busno = 0, ret; |
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125 | | - |
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126 | | - pr_info("PCI: Probing PCI hardware\n"); |
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127 | | - |
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128 | | - /* Scan all of the recorded PCI controllers. */ |
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129 | | - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { |
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130 | | - pci_ctrl->last_busno = 0xff; |
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131 | | - INIT_LIST_HEAD(&resources); |
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132 | | - pci_controller_apertures(pci_ctrl, &resources); |
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133 | | - bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, |
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134 | | - pci_ctrl->ops, pci_ctrl, &resources); |
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135 | | - if (!bus) |
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136 | | - continue; |
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137 | | - |
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138 | | - pci_ctrl->bus = bus; |
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139 | | - pci_ctrl->last_busno = bus->busn_res.end; |
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140 | | - if (next_busno <= pci_ctrl->last_busno) |
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141 | | - next_busno = pci_ctrl->last_busno+1; |
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142 | | - } |
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143 | | - pci_bus_count = next_busno; |
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144 | | - ret = platform_pcibios_fixup(); |
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145 | | - if (ret) |
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146 | | - return ret; |
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147 | | - |
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148 | | - for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { |
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149 | | - if (pci_ctrl->bus) |
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150 | | - pci_bus_add_devices(pci_ctrl->bus); |
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151 | | - } |
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152 | | - |
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153 | | - return 0; |
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154 | | -} |
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155 | | - |
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156 | | -subsys_initcall(pcibios_init); |
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157 | | - |
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158 | 61 | void pcibios_fixup_bus(struct pci_bus *bus) |
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159 | 62 | { |
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160 | 63 | if (bus->parent) { |
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161 | 64 | /* This is a subordinate bridge */ |
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162 | 65 | pci_read_bridge_bases(bus); |
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163 | 66 | } |
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164 | | -} |
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165 | | - |
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166 | | -void pcibios_set_master(struct pci_dev *dev) |
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167 | | -{ |
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168 | | - /* No special bus mastering setup handling */ |
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169 | | -} |
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170 | | - |
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171 | | -int pcibios_enable_device(struct pci_dev *dev, int mask) |
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172 | | -{ |
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173 | | - u16 cmd, old_cmd; |
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174 | | - int idx; |
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175 | | - struct resource *r; |
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176 | | - |
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177 | | - pci_read_config_word(dev, PCI_COMMAND, &cmd); |
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178 | | - old_cmd = cmd; |
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179 | | - for (idx=0; idx<6; idx++) { |
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180 | | - r = &dev->resource[idx]; |
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181 | | - if (!r->start && r->end) { |
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182 | | - pci_err(dev, "can't enable device: resource collisions\n"); |
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183 | | - return -EINVAL; |
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184 | | - } |
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185 | | - if (r->flags & IORESOURCE_IO) |
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186 | | - cmd |= PCI_COMMAND_IO; |
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187 | | - if (r->flags & IORESOURCE_MEM) |
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188 | | - cmd |= PCI_COMMAND_MEMORY; |
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189 | | - } |
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190 | | - if (cmd != old_cmd) { |
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191 | | - pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd); |
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192 | | - pci_write_config_word(dev, PCI_COMMAND, cmd); |
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193 | | - } |
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194 | | - |
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195 | | - return 0; |
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196 | 67 | } |
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197 | 68 | |
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198 | 69 | /* |
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