~hc/RK356X_SDK_RELEASE.git

..	..	@@ -6,6 +6,7 @@
6	6	#ifndef __ARCH_PARISC_CACHE_H
7	7	#define __ARCH_PARISC_CACHE_H
8	8
	9	+#include <asm/alternative.h>
9	10
10	11	/*
11	12	* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
..	..	@@ -21,10 +22,7 @@
21	22
22	23	#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
23	24
24		-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
25		-
26		-/* Read-only memory is marked before mark_rodata_ro() is called. */
27		-#define __ro_after_init __read_mostly
	25	+#define __read_mostly __section(".data..read_mostly")
28	26
29	27	void parisc_cache_init(void); /* initializes cache-flushing */
30	28	void disable_sr_hashing_asm(int); /* low level support for above */
..	..	@@ -41,9 +39,24 @@
41	39	extern struct pdc_cache_info cache_info;
42	40	void parisc_setup_cache_timing(void);
43	41
44		-#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
45		-#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
46		-#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
	42	+#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \
	43	+ ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
	44	+ : : "r" (addr) : "memory")
	45	+#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \
	46	+ ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
	47	+ ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
	48	+ : : "r" (addr) : "memory")
	49	+#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \
	50	+ ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
	51	+ : : "r" (addr) : "memory")
	52	+
	53	+#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
	54	+ ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
	55	+ ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
	56	+ : : "r" (addr) : "memory")
	57	+#define asm_io_sync() asm volatile("sync" \
	58	+ ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
	59	+ ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
47	60
48	61	#endif /* ! __ASSEMBLY__ */
49	62