| .. | .. |
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| 8 | 8 | #ifndef __ASM_SN_INTR_H |
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| 9 | 9 | #define __ASM_SN_INTR_H |
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| 10 | 10 | |
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| 11 | | -/* Number of interrupt levels associated with each interrupt register. */ |
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| 12 | | -#define N_INTPEND_BITS 64 |
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| 13 | | - |
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| 14 | | -#define INT_PEND0_BASELVL 0 |
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| 15 | | -#define INT_PEND1_BASELVL 64 |
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| 16 | | - |
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| 17 | | -#define N_INTPENDJUNK_BITS 8 |
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| 18 | | -#define INTPENDJUNK_CLRBIT 0x80 |
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| 19 | | - |
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| 20 | 11 | /* |
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| 21 | 12 | * Macros to manipulate the interrupt register on the calling hub chip. |
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| 22 | 13 | */ |
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| .. | .. |
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| 84 | 75 | #define CPU_RESCHED_B_IRQ 8 |
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| 85 | 76 | #define CPU_CALL_A_IRQ 9 |
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| 86 | 77 | #define CPU_CALL_B_IRQ 10 |
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| 87 | | -#define MSC_MESG_INTR 11 |
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| 88 | | -#define BASE_PCI_IRQ 12 |
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| 89 | | - |
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| 90 | | -/* |
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| 91 | | - * INT_PEND0 again, bits determined by hardware / hardcoded: |
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| 92 | | - */ |
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| 93 | | -#define SDISK_INTR 63 /* SABLE name */ |
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| 94 | | -#define IP_PEND0_6_63 63 /* What is this bit? */ |
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| 95 | 78 | |
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| 96 | 79 | /* |
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| 97 | 80 | * INT_PEND1 hard-coded bits: |
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