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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/arch/mips/include/asm/asmmacro.h
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@@ -44,7 +44,7 @@
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 	.endm
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 #endif
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-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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+#ifdef CONFIG_CPU_HAS_DIEI
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 	.macro	local_irq_enable reg=t0
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 	ei
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 	irq_enable_hazard
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@@ -54,7 +54,7 @@
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 	di
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 	irq_disable_hazard
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 	.endm
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-#else
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+#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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 	.macro	local_irq_enable reg=t0
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 	mfc0	\reg, CP0_STATUS
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 	ori	\reg, \reg, 1
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@@ -63,7 +63,7 @@
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 	.endm
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 	.macro	local_irq_disable reg=t0
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-#ifdef CONFIG_PREEMPT
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+#ifdef CONFIG_PREEMPTION
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 	lw      \reg, TI_PRE_COUNT($28)
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 	addi    \reg, \reg, 1
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 	sw      \reg, TI_PRE_COUNT($28)
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@@ -73,13 +73,13 @@
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 	xori	\reg, \reg, 1
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 	mtc0	\reg, CP0_STATUS
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 	irq_disable_hazard
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-#ifdef CONFIG_PREEMPT
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+#ifdef CONFIG_PREEMPTION
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 	lw      \reg, TI_PRE_COUNT($28)
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 	addi    \reg, \reg, -1
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 	sw      \reg, TI_PRE_COUNT($28)
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 #endif
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 	.endm
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-#endif /* CONFIG_CPU_MIPSR2 */
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+#endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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 	.macro	fpu_save_16even thread tmp=t0
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 	.set	push
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@@ -131,7 +131,7 @@
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 	.macro	fpu_save_double thread status tmp
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 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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-		defined(CONFIG_CPU_MIPSR6)
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
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 	sll	\tmp, \status, 5
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 	bgez	\tmp, 10f
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 	fpu_save_16odd \thread
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@@ -190,7 +190,7 @@
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 	.macro	fpu_restore_double thread status tmp
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 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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-		defined(CONFIG_CPU_MIPSR6)
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+    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
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 	sll	\tmp, \status, 5
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 	bgez	\tmp, 10f				# 16 register mode?
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@@ -200,16 +200,17 @@
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 	fpu_restore_16even \thread \tmp
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 	.endm
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-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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+    defined(CONFIG_CPU_MIPSR6)
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 	.macro	_EXT	rd, rs, p, s
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 	ext	\rd, \rs, \p, \s
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 	.endm
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-#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
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+#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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 	.macro	_EXT	rd, rs, p, s
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 	srl	\rd, \rs, \p
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 	andi	\rd, \rd, (1 << \s) - 1
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 	.endm
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-#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
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+#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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 /*
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  * Temporary until all gas have MT ASE support