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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/arch/arm/mach-tegra/sleep-tegra20.S
....@@ -1,21 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
34  * Copyright (c) 2011, Google, Inc.
45  *
56  * Author: Colin Cross <ccross@android.com>
67  *         Gary King <gking@nvidia.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms and conditions of the GNU General Public License,
10
- * version 2, as published by the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope it will be useful, but WITHOUT
13
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15
- * more details.
16
- *
17
- * You should have received a copy of the GNU General Public License
18
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
198  */
209 
2110 #include <linux/linkage.h>
....@@ -28,11 +17,11 @@
2817 #include <asm/cache.h>
2918 
3019 #include "irammap.h"
20
+#include "reset.h"
3121 #include "sleep.h"
3222 
3323 #define EMC_CFG				0xc
3424 #define EMC_ADR_CFG			0x10
35
-#define EMC_REFRESH			0x70
3625 #define EMC_NOP				0xdc
3726 #define EMC_SELF_REF			0xe0
3827 #define EMC_REQ_CTRL			0x2b0
....@@ -98,10 +87,6 @@
9887 ENTRY(tegra20_cpu_shutdown)
9988 	cmp	r0, #0
10089 	reteq	lr			@ must not be called for CPU 0
101
-	mov32	r1, TEGRA_IRAM_RESET_BASE_VIRT
102
-	ldr	r2, =__tegra20_cpu1_resettable_status_offset
103
-	mov	r12, #CPU_RESETTABLE
104
-	strb	r12, [r1, r2]
10590 
10691 	cpu_to_halt_reg r1, r0
10792 	ldr	r3, =TEGRA_FLOW_CTRL_VIRT
....@@ -124,107 +109,6 @@
124109 #endif
125110 
126111 #ifdef CONFIG_PM_SLEEP
127
-/*
128
- * tegra_pen_lock
129
- *
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- * spinlock implementation with no atomic test-and-set and no coherence
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- * using Peterson's algorithm on strongly-ordered registers
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- * used to synchronize a cpu waking up from wfi with entering lp2 on idle
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- *
134
- * The reference link of Peterson's algorithm:
135
- * http://en.wikipedia.org/wiki/Peterson's_algorithm
136
- *
137
- * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
138
- * on cpu 0:
139
- * r2 = flag[0] (in SCRATCH38)
140
- * r3 = flag[1] (in SCRATCH39)
141
- * on cpu1:
142
- * r2 = flag[1] (in SCRATCH39)
143
- * r3 = flag[0] (in SCRATCH38)
144
- *
145
- * must be called with MMU on
146
- * corrupts r0-r3, r12
147
- */
148
-ENTRY(tegra_pen_lock)
149
-	mov32	r3, TEGRA_PMC_VIRT
150
-	cpu_id	r0
151
-	add	r1, r3, #PMC_SCRATCH37
152
-	cmp	r0, #0
153
-	addeq	r2, r3, #PMC_SCRATCH38
154
-	addeq	r3, r3, #PMC_SCRATCH39
155
-	addne	r2, r3, #PMC_SCRATCH39
156
-	addne	r3, r3, #PMC_SCRATCH38
157
-
158
-	mov	r12, #1
159
-	str	r12, [r2]		@ flag[cpu] = 1
160
-	dsb
161
-	str	r12, [r1]		@ !turn = cpu
162
-1:	dsb
163
-	ldr	r12, [r3]
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-	cmp	r12, #1			@ flag[!cpu] == 1?
165
-	ldreq	r12, [r1]
166
-	cmpeq	r12, r0			@ !turn == cpu?
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-	beq	1b			@ while !turn == cpu && flag[!cpu] == 1
168
-
169
-	ret	lr			@ locked
170
-ENDPROC(tegra_pen_lock)
171
-
172
-ENTRY(tegra_pen_unlock)
173
-	dsb
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-	mov32	r3, TEGRA_PMC_VIRT
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-	cpu_id	r0
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-	cmp	r0, #0
177
-	addeq	r2, r3, #PMC_SCRATCH38
178
-	addne	r2, r3, #PMC_SCRATCH39
179
-	mov	r12, #0
180
-	str	r12, [r2]
181
-	ret     lr
182
-ENDPROC(tegra_pen_unlock)
183
-
184
-/*
185
- * tegra20_cpu_clear_resettable(void)
186
- *
187
- * Called to clear the "resettable soon" flag in IRAM variable when
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- * it is expected that the secondary CPU will be idle soon.
189
- */
190
-ENTRY(tegra20_cpu_clear_resettable)
191
-	mov32	r1, TEGRA_IRAM_RESET_BASE_VIRT
192
-	ldr	r2, =__tegra20_cpu1_resettable_status_offset
193
-	mov	r12, #CPU_NOT_RESETTABLE
194
-	strb	r12, [r1, r2]
195
-	ret	lr
196
-ENDPROC(tegra20_cpu_clear_resettable)
197
-
198
-/*
199
- * tegra20_cpu_set_resettable_soon(void)
200
- *
201
- * Called to set the "resettable soon" flag in IRAM variable when
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- * it is expected that the secondary CPU will be idle soon.
203
- */
204
-ENTRY(tegra20_cpu_set_resettable_soon)
205
-	mov32	r1, TEGRA_IRAM_RESET_BASE_VIRT
206
-	ldr	r2, =__tegra20_cpu1_resettable_status_offset
207
-	mov	r12, #CPU_RESETTABLE_SOON
208
-	strb	r12, [r1, r2]
209
-	ret	lr
210
-ENDPROC(tegra20_cpu_set_resettable_soon)
211
-
212
-/*
213
- * tegra20_cpu_is_resettable_soon(void)
214
- *
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- * Returns true if the "resettable soon" flag in IRAM variable has been
216
- * set because it is expected that the secondary CPU will be idle soon.
217
- */
218
-ENTRY(tegra20_cpu_is_resettable_soon)
219
-	mov32	r1, TEGRA_IRAM_RESET_BASE_VIRT
220
-	ldr	r2, =__tegra20_cpu1_resettable_status_offset
221
-	ldrb	r12, [r1, r2]
222
-	cmp	r12, #CPU_RESETTABLE_SOON
223
-	moveq	r0, #1
224
-	movne	r0, #0
225
-	ret	lr
226
-ENDPROC(tegra20_cpu_is_resettable_soon)
227
-
228112 /*
229113  * tegra20_sleep_core_finish(unsigned long v2p)
230114  *
....@@ -249,68 +133,6 @@
249133 
250134 	ret	r3
251135 ENDPROC(tegra20_sleep_core_finish)
252
-
253
-/*
254
- * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
255
- *
256
- * Enters WFI on secondary CPU by exiting coherency.
257
- */
258
-ENTRY(tegra20_sleep_cpu_secondary_finish)
259
-	stmfd	sp!, {r4-r11, lr}
260
-
261
-	mrc	p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
262
-
263
-	/* Flush and disable the L1 data cache */
264
-	mov	r0, #TEGRA_FLUSH_CACHE_LOUIS
265
-	bl	tegra_disable_clean_inv_dcache
266
-
267
-	mov32	r0, TEGRA_IRAM_RESET_BASE_VIRT
268
-	ldr	r4, =__tegra20_cpu1_resettable_status_offset
269
-	mov	r3, #CPU_RESETTABLE
270
-	strb	r3, [r0, r4]
271
-
272
-	bl	tegra_cpu_do_idle
273
-
274
-	/*
275
-	 * cpu may be reset while in wfi, which will return through
276
-	 * tegra_resume to cpu_resume
277
-	 * or interrupt may wake wfi, which will return here
278
-	 * cpu state is unchanged - MMU is on, cache is on, coherency
279
-	 * is off, and the data cache is off
280
-	 *
281
-	 * r11 contains the original actlr
282
-	 */
283
-
284
-	bl	tegra_pen_lock
285
-
286
-	mov32	r0, TEGRA_IRAM_RESET_BASE_VIRT
287
-	ldr	r4, =__tegra20_cpu1_resettable_status_offset
288
-	mov	r3, #CPU_NOT_RESETTABLE
289
-	strb	r3, [r0, r4]
290
-
291
-	bl	tegra_pen_unlock
292
-
293
-	/* Re-enable the data cache */
294
-	mrc	p15, 0, r10, c1, c0, 0
295
-	orr	r10, r10, #CR_C
296
-	mcr	p15, 0, r10, c1, c0, 0
297
-	isb
298
-
299
-	mcr	p15, 0, r11, c1, c0, 1	@ reenable coherency
300
-
301
-	/* Invalidate the TLBs & BTAC */
302
-	mov	r1, #0
303
-	mcr	p15, 0, r1, c8, c3, 0	@ invalidate shared TLBs
304
-	mcr	p15, 0, r1, c7, c1, 6	@ invalidate shared BTAC
305
-	dsb
306
-	isb
307
-
308
-	/* the cpu was running with coherency disabled,
309
-	 * caches may be out of date */
310
-	bl	v7_flush_kern_cache_louis
311
-
312
-	ldmfd	sp!, {r4 - r11, pc}
313
-ENDPROC(tegra20_sleep_cpu_secondary_finish)
314136 
315137 /*
316138  * tegra20_tear_down_cpu
....@@ -397,7 +219,6 @@
397219 	mov	r1, #1
398220 	str	r1, [r0, #EMC_NOP]
399221 	str	r1, [r0, #EMC_NOP]
400
-	str	r1, [r0, #EMC_REFRESH]
401222 
402223 	emc_device_mask r1, r0
403224