forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/arch/arm/boot/dts/tegra30-colibri.dtsi
....@@ -1,27 +1,22 @@
11 // SPDX-License-Identifier: GPL-2.0
2
-#include <dt-bindings/input/input.h>
32 #include "tegra30.dtsi"
43 
54 /*
65  * Toradex Colibri T30 Module Device Tree
7
- * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
6
+ * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
87  */
98 / {
10
-	model = "Toradex Colibri T30";
11
-	compatible = "toradex,colibri_t30", "nvidia,tegra30";
12
-
139 	memory@80000000 {
1410 		reg = <0x80000000 0x40000000>;
1511 	};
1612 
1713 	host1x@50000000 {
1814 		hdmi@54280000 {
19
-			vdd-supply = <&avdd_hdmi_3v3_reg>;
20
-			pll-supply = <&avdd_hdmi_pll_1v8_reg>;
21
-
15
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
2216 			nvidia,hpd-gpio =
2317 				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
24
-			nvidia,ddc-i2c-bus = <&hdmiddc>;
18
+			pll-supply = <&reg_1v8_avdd_hdmi_pll>;
19
+			vdd-supply = <&reg_3v3_avdd_hdmi>;
2520 		};
2621 	};
2722 
....@@ -31,21 +26,171 @@
3126 
3227 		state_default: pinmux {
3328 			/* Analogue Audio (On-module) */
34
-			clk1_out_pw4 {
29
+			clk1-out-pw4 {
3530 				nvidia,pins = "clk1_out_pw4";
3631 				nvidia,function = "extperiph1";
3732 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
3833 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
3934 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
4035 			};
41
-			dap3_fs_pp0 {
42
-				nvidia,pins =	"dap3_fs_pp0",
43
-						"dap3_sclk_pp3",
44
-						"dap3_din_pp1",
45
-						"dap3_dout_pp2";
36
+			dap3-fs-pp0 {
37
+				nvidia,pins = "dap3_fs_pp0",
38
+					      "dap3_sclk_pp3",
39
+					      "dap3_din_pp1",
40
+					      "dap3_dout_pp2";
4641 				nvidia,function = "i2s2";
4742 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4843 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
44
+			};
45
+
46
+			/* Colibri Address/Data Bus (GMI) */
47
+			gmi-ad0-pg0 {
48
+				nvidia,pins = "gmi_ad0_pg0",
49
+					      "gmi_ad2_pg2",
50
+					      "gmi_ad3_pg3",
51
+					      "gmi_ad4_pg4",
52
+					      "gmi_ad5_pg5",
53
+					      "gmi_ad6_pg6",
54
+					      "gmi_ad7_pg7",
55
+					      "gmi_ad8_ph0",
56
+					      "gmi_ad9_ph1",
57
+					      "gmi_ad10_ph2",
58
+					      "gmi_ad11_ph3",
59
+					      "gmi_ad12_ph4",
60
+					      "gmi_ad13_ph5",
61
+					      "gmi_ad14_ph6",
62
+					      "gmi_ad15_ph7",
63
+					      "gmi_adv_n_pk0",
64
+					      "gmi_clk_pk1",
65
+					      "gmi_cs4_n_pk2",
66
+					      "gmi_cs2_n_pk3",
67
+					      "gmi_iordy_pi5",
68
+					      "gmi_oe_n_pi1",
69
+					      "gmi_wait_pi7",
70
+					      "gmi_wr_n_pi0",
71
+					      "dap1_fs_pn0",
72
+					      "dap1_din_pn1",
73
+					      "dap1_dout_pn2",
74
+					      "dap1_sclk_pn3",
75
+					      "dap2_fs_pa2",
76
+					      "dap2_sclk_pa3",
77
+					      "dap2_din_pa4",
78
+					      "dap2_dout_pa5",
79
+					      "spi1_sck_px5",
80
+					      "spi1_mosi_px4",
81
+					      "spi1_cs0_n_px6",
82
+					      "spi2_cs0_n_px3",
83
+					      "spi2_miso_px1",
84
+					      "spi2_mosi_px0",
85
+					      "spi2_sck_px2",
86
+					      "uart2_cts_n_pj5",
87
+					      "uart2_rts_n_pj6";
88
+				nvidia,function = "gmi";
89
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
91
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92
+			};
93
+			/* Further pins may be used as GPIOs */
94
+			dap4-din-pp5 {
95
+				nvidia,pins = "dap4_din_pp5",
96
+					      "dap4_dout_pp6",
97
+					      "dap4_fs_pp4",
98
+					      "dap4_sclk_pp7",
99
+					      "pbb7",
100
+					      "sdmmc1_clk_pz0",
101
+					      "sdmmc1_cmd_pz1",
102
+					      "sdmmc1_dat0_py7",
103
+					      "sdmmc1_dat1_py6",
104
+					      "sdmmc1_dat3_py4",
105
+					      "uart3_cts_n_pa1",
106
+					      "uart3_txd_pw6",
107
+					      "uart3_rxd_pw7";
108
+				nvidia,function = "rsvd2";
109
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
111
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
112
+			};
113
+			lcd-d18-pm2 {
114
+				nvidia,pins = "lcd_d18_pm2",
115
+					      "lcd_d19_pm3",
116
+					      "lcd_d20_pm4",
117
+					      "lcd_d21_pm5",
118
+					      "lcd_d22_pm6",
119
+					      "lcd_d23_pm7",
120
+					      "lcd_dc0_pn6",
121
+					      "pex_l2_clkreq_n_pcc7";
122
+				nvidia,function = "rsvd3";
123
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
124
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
125
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
126
+			};
127
+			lcd-cs0-n-pn4 {
128
+				nvidia,pins = "lcd_cs0_n_pn4",
129
+					      "lcd_sdin_pz2",
130
+					      "pu0",
131
+					      "pu1",
132
+					      "pu2",
133
+					      "pu3",
134
+					      "pu4",
135
+					      "pu5",
136
+					      "pu6",
137
+					      "spi1_miso_px7",
138
+					      "uart3_rts_n_pc0";
139
+				nvidia,function = "rsvd4";
140
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
142
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143
+			};
144
+			lcd-pwr0-pb2 {
145
+				nvidia,pins = "lcd_pwr0_pb2",
146
+					      "lcd_sck_pz4",
147
+					      "lcd_sdout_pn5",
148
+					      "lcd_wr_n_pz3";
149
+				nvidia,function = "hdcp";
150
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
151
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
152
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153
+			};
154
+			pbb4 {
155
+				nvidia,pins = "pbb4",
156
+					      "pbb5",
157
+					      "pbb6";
158
+				nvidia,function = "displayb";
159
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
161
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
162
+			};
163
+			/* Multiplexed RDnWR and therefore disabled */
164
+			lcd-cs1-n-pw0 {
165
+				nvidia,pins = "lcd_cs1_n_pw0";
166
+				nvidia,function = "rsvd4";
167
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
168
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
169
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
170
+			};
171
+			/* Multiplexed GMI_CLK and therefore disabled */
172
+			owr {
173
+				nvidia,pins = "owr";
174
+				nvidia,function = "rsvd3";
175
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
176
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
177
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
178
+			};
179
+			/* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
180
+			sdmmc3-dat4-pd1 {
181
+				nvidia,pins = "sdmmc3_dat4_pd1";
182
+				nvidia,function = "sdmmc3";
183
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
184
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
185
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
186
+			};
187
+			/* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
188
+			sdmmc3-dat5-pd0 {
189
+				nvidia,pins = "sdmmc3_dat5_pd0";
190
+				nvidia,function = "sdmmc3";
191
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
192
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
193
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
49194 			};
50195 
51196 			/* Colibri BL_ON */
....@@ -57,7 +202,7 @@
57202 			};
58203 
59204 			/* Colibri Backlight PWM<A> */
60
-			sdmmc3_dat3_pb4 {
205
+			sdmmc3-dat3-pb4 {
61206 				nvidia,pins = "sdmmc3_dat3_pb4";
62207 				nvidia,function = "pwm0";
63208 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
....@@ -65,7 +210,7 @@
65210 			};
66211 
67212 			/* Colibri CAN_INT */
68
-			kb_row8_ps0 {
213
+			kb-row8-ps0 {
69214 				nvidia,pins = "kb_row8_ps0";
70215 				nvidia,function = "kbc";
71216 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
....@@ -73,26 +218,133 @@
73218 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
74219 			};
75220 
76
-			/*
77
-			 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
78
-			 * todays display need DE, disable LCD_M1
79
-			 */
80
-			lcd_m1_pw1 {
81
-				nvidia,pins = "lcd_m1_pw1";
82
-				nvidia,function = "rsvd3";
221
+			/* Colibri DDC */
222
+			ddc-scl-pv4 {
223
+				nvidia,pins = "ddc_scl_pv4",
224
+					      "ddc_sda_pv5";
225
+				nvidia,function = "i2c4";
83226 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84227 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
85228 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86229 			};
87230 
231
+			/* Colibri EXT_IO* */
232
+			gen2-i2c-scl-pt5 {
233
+				nvidia,pins = "gen2_i2c_scl_pt5",
234
+					      "gen2_i2c_sda_pt6";
235
+				nvidia,function = "rsvd4";
236
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
237
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
239
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
240
+			};
241
+			spdif-in-pk6 {
242
+				nvidia,pins =	"spdif_in_pk6";
243
+				nvidia,function = "hda";
244
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
246
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247
+			};
248
+
249
+			/* Colibri GPIO */
250
+			clk2-out-pw5 {
251
+				nvidia,pins = "clk2_out_pw5",
252
+					      "pcc2",
253
+					      "pv3",
254
+					      "sdmmc1_dat2_py5";
255
+				nvidia,function = "rsvd2";
256
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
259
+			};
260
+			lcd-pwr1-pc1 {
261
+				nvidia,pins = "lcd_pwr1_pc1",
262
+					      "pex_l1_clkreq_n_pdd6",
263
+					      "pex_l1_rst_n_pdd5";
264
+				nvidia,function = "rsvd3";
265
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
266
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
267
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268
+			};
269
+			pv1 {
270
+				nvidia,pins = "pv1",
271
+					      "sdmmc3_dat0_pb7",
272
+					      "sdmmc3_dat1_pb6";
273
+				nvidia,function = "rsvd1";
274
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
276
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
277
+			};
278
+
279
+			/* Colibri HOTPLUG_DETECT (HDMI) */
280
+			hdmi-int-pn7 {
281
+				nvidia,pins = "hdmi_int_pn7";
282
+				nvidia,function = "hdmi";
283
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
285
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
286
+			};
287
+
288
+			/* Colibri I2C */
289
+			gen1-i2c-scl-pc4 {
290
+				nvidia,pins = "gen1_i2c_scl_pc4",
291
+					      "gen1_i2c_sda_pc5";
292
+				nvidia,function = "i2c1";
293
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
294
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
295
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
296
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
297
+			};
298
+
299
+			/* Colibri LCD (L_* resp. LDD<*>) */
300
+			lcd-d0-pe0 {
301
+				nvidia,pins = "lcd_d0_pe0",
302
+					      "lcd_d1_pe1",
303
+					      "lcd_d2_pe2",
304
+					      "lcd_d3_pe3",
305
+					      "lcd_d4_pe4",
306
+					      "lcd_d5_pe5",
307
+					      "lcd_d6_pe6",
308
+					      "lcd_d7_pe7",
309
+					      "lcd_d8_pf0",
310
+					      "lcd_d9_pf1",
311
+					      "lcd_d10_pf2",
312
+					      "lcd_d11_pf3",
313
+					      "lcd_d12_pf4",
314
+					      "lcd_d13_pf5",
315
+					      "lcd_d14_pf6",
316
+					      "lcd_d15_pf7",
317
+					      "lcd_d16_pm0",
318
+					      "lcd_d17_pm1",
319
+					      "lcd_de_pj1",
320
+					      "lcd_hsync_pj3",
321
+					      "lcd_pclk_pb3",
322
+					      "lcd_vsync_pj4";
323
+				nvidia,function = "displaya";
324
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
325
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
326
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
327
+			};
328
+			/*
329
+			 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
330
+			 * today's display need DE, disable LCD_M1
331
+			 */
332
+			lcd-m1-pw1 {
333
+				nvidia,pins = "lcd_m1_pw1";
334
+				nvidia,function = "rsvd3";
335
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
336
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
337
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
338
+			};
339
+
88340 			/* Colibri MMC */
89
-			kb_row10_ps2 {
341
+			kb-row10-ps2 {
90342 				nvidia,pins = "kb_row10_ps2";
91343 				nvidia,function = "sdmmc2";
92344 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93345 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
94346 			};
95
-			kb_row11_ps3 {
347
+			kb-row11-ps3 {
96348 				nvidia,pins = "kb_row11_ps3",
97349 					      "kb_row12_ps4",
98350 					      "kb_row13_ps5",
....@@ -102,9 +354,108 @@
102354 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
103355 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
104356 			};
357
+			/* Colibri MMC_CD */
358
+			gmi-wp-n-pc7 {
359
+				nvidia,pins = "gmi_wp_n_pc7";
360
+				nvidia,function = "rsvd1";
361
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
362
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
363
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364
+			};
365
+			/* Multiplexed and therefore disabled */
366
+			cam-mclk-pcc0 {
367
+				nvidia,pins =	"cam_mclk_pcc0";
368
+				nvidia,function = "vi_alt3";
369
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
370
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
371
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
372
+			};
373
+			cam-i2c-scl-pbb1 {
374
+				nvidia,pins = "cam_i2c_scl_pbb1",
375
+					      "cam_i2c_sda_pbb2";
376
+				nvidia,function = "rsvd3";
377
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
378
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
379
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
380
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381
+			};
382
+			pbb0 {
383
+				nvidia,pins = "pbb0",
384
+					      "pcc1";
385
+				nvidia,function = "rsvd2";
386
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
387
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
388
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389
+			};
390
+			pbb3 {
391
+				nvidia,pins = "pbb3";
392
+				nvidia,function = "displayb";
393
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
394
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
395
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396
+			};
397
+
398
+			/* Colibri nRESET_OUT */
399
+			gmi-rst-n-pi4 {
400
+				nvidia,pins = "gmi_rst_n_pi4";
401
+				nvidia,function = "gmi";
402
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404
+			};
405
+
406
+			/*
407
+			 * Colibri Parallel Camera (Optional)
408
+			 * pins multiplexed with others and therefore disabled
409
+			 */
410
+			vi-vsync-pd6 {
411
+				nvidia,pins = "vi_d0_pt4",
412
+					      "vi_d1_pd5",
413
+					      "vi_d2_pl0",
414
+					      "vi_d3_pl1",
415
+					      "vi_d4_pl2",
416
+					      "vi_d5_pl3",
417
+					      "vi_d6_pl4",
418
+					      "vi_d7_pl5",
419
+					      "vi_d8_pl6",
420
+					      "vi_d9_pl7",
421
+					      "vi_d10_pt2",
422
+					      "vi_d11_pt3",
423
+					      "vi_hsync_pd7",
424
+					      "vi_mclk_pt1",
425
+					      "vi_pclk_pt0",
426
+					      "vi_vsync_pd6";
427
+				nvidia,function = "vi";
428
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
429
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
430
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431
+			};
432
+
433
+			/* Colibri PWM<B> */
434
+			sdmmc3-dat2-pb5 {
435
+				nvidia,pins = "sdmmc3_dat2_pb5";
436
+				nvidia,function = "pwm1";
437
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
439
+			};
440
+
441
+			/* Colibri PWM<C> */
442
+			sdmmc3-clk-pa6 {
443
+				nvidia,pins = "sdmmc3_clk_pa6";
444
+				nvidia,function = "pwm2";
445
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
446
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
447
+			};
448
+
449
+			/* Colibri PWM<D> */
450
+			sdmmc3-cmd-pa7 {
451
+				nvidia,pins = "sdmmc3_cmd_pa7";
452
+				nvidia,function = "pwm3";
453
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
455
+			};
105456 
106457 			/* Colibri SSP */
107
-			ulpi_clk_py0 {
458
+			ulpi-clk-py0 {
108459 				nvidia,pins = "ulpi_clk_py0",
109460 					      "ulpi_dir_py1",
110461 					      "ulpi_nxt_py2",
....@@ -113,16 +464,18 @@
113464 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114465 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
115466 			};
116
-			sdmmc3_dat6_pd3 {
467
+			/* Multiplexed SSPFRM, SSPTXD and therefore disabled */
468
+			sdmmc3-dat6-pd3 {
117469 				nvidia,pins = "sdmmc3_dat6_pd3",
118470 					      "sdmmc3_dat7_pd4";
119471 				nvidia,function = "spdif";
120
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
121473 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
474
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
122475 			};
123476 
124
-			/* Colibri UART_A */
125
-			ulpi_data0 {
477
+			/* Colibri UART-A */
478
+			ulpi-data0 {
126479 				nvidia,pins = "ulpi_data0_po1",
127480 					      "ulpi_data1_po2",
128481 					      "ulpi_data2_po3",
....@@ -136,8 +489,8 @@
136489 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
137490 			};
138491 
139
-			/* Colibri UART_B */
140
-			gmi_a16_pj7 {
492
+			/* Colibri UART-B */
493
+			gmi-a16-pj7 {
141494 				nvidia,pins = "gmi_a16_pj7",
142495 					      "gmi_a17_pb0",
143496 					      "gmi_a18_pb1",
....@@ -147,8 +500,8 @@
147500 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
148501 			};
149502 
150
-			/* Colibri UART_C */
151
-			uart2_rxd {
503
+			/* Colibri UART-C */
504
+			uart2-rxd {
152505 				nvidia,pins = "uart2_rxd_pc3",
153506 					      "uart2_txd_pc2";
154507 				nvidia,function = "uartb";
....@@ -156,15 +509,53 @@
156509 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
157510 			};
158511 
159
-			/* eMMC */
160
-			sdmmc4_clk_pcc4 {
512
+			/* Colibri USBC_DET */
513
+			spdif-out-pk5 {
514
+				nvidia,pins =	"spdif_out_pk5";
515
+				nvidia,function = "rsvd2";
516
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
517
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
518
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
519
+			};
520
+
521
+			/* Colibri USBH_PEN */
522
+			spi2-cs1-n-pw2 {
523
+				nvidia,pins = "spi2_cs1_n_pw2";
524
+				nvidia,function = "spi2_alt";
525
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
526
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
527
+			};
528
+
529
+			/* Colibri USBH_OC */
530
+			spi2-cs2-n-pw3 {
531
+				nvidia,pins = "spi2_cs2_n_pw3";
532
+				nvidia,function = "spi2_alt";
533
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
534
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
535
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
536
+			};
537
+
538
+			/* Colibri VGA not supported and therefore disabled */
539
+			crt-hsync-pv6 {
540
+				nvidia,pins = "crt_hsync_pv6",
541
+					      "crt_vsync_pv7";
542
+				nvidia,function = "rsvd2";
543
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
544
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
545
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
546
+			};
547
+
548
+			/* eMMC (On-module) */
549
+			sdmmc4-clk-pcc4 {
161550 				nvidia,pins = "sdmmc4_clk_pcc4",
551
+					      "sdmmc4_cmd_pt7",
162552 					      "sdmmc4_rst_n_pcc3";
163553 				nvidia,function = "sdmmc4";
164554 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165555 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
556
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
166557 			};
167
-			sdmmc4_dat0_paa0 {
558
+			sdmmc4-dat0-paa0 {
168559 				nvidia,pins = "sdmmc4_dat0_paa0",
169560 					      "sdmmc4_dat1_paa1",
170561 					      "sdmmc4_dat2_paa2",
....@@ -176,17 +567,111 @@
176567 				nvidia,function = "sdmmc4";
177568 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
178569 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
570
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
571
+			};
572
+
573
+			/* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
574
+			pex-l0-rst-n-pdd1 {
575
+				nvidia,pins = "pex_l0_rst_n_pdd1",
576
+					      "pex_wake_n_pdd3";
577
+				nvidia,function = "rsvd3";
578
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
579
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
580
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
581
+			};
582
+			/* LAN_V_BUS, LAN_RESET# (On-module) */
583
+			pex-l0-clkreq-n-pdd2 {
584
+				nvidia,pins = "pex_l0_clkreq_n_pdd2",
585
+					      "pex_l0_prsnt_n_pdd0";
586
+				nvidia,function = "rsvd3";
587
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
589
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
590
+			};
591
+
592
+			/* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
593
+			pex-l2-rst-n-pcc6 {
594
+				nvidia,pins = "pex_l2_rst_n_pcc6",
595
+					      "pex_l2_prsnt_n_pdd7";
596
+				nvidia,function = "rsvd3";
597
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
599
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600
+			};
601
+
602
+			/* Not connected and therefore disabled */
603
+			clk1-req-pee2 {
604
+				nvidia,pins = "clk1_req_pee2",
605
+					      "pex_l1_prsnt_n_pdd4";
606
+				nvidia,function = "rsvd3";
607
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
608
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
609
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
610
+			};
611
+			clk2-req-pcc5 {
612
+				nvidia,pins = "clk2_req_pcc5",
613
+					      "clk3_out_pee0",
614
+					      "clk3_req_pee1",
615
+					      "clk_32k_out_pa0",
616
+					      "hdmi_cec_pee3",
617
+					      "sys_clk_req_pz5";
618
+				nvidia,function = "rsvd2";
619
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
620
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
621
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
622
+			};
623
+			gmi-dqs-pi2 {
624
+				nvidia,pins = "gmi_dqs_pi2",
625
+					      "kb_col2_pq2",
626
+					      "kb_col3_pq3",
627
+					      "kb_col4_pq4",
628
+					      "kb_col5_pq5",
629
+					      "kb_row4_pr4";
630
+				nvidia,function = "rsvd4";
631
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
632
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
633
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
634
+			};
635
+			kb-col0-pq0 {
636
+				nvidia,pins = "kb_col0_pq0",
637
+					      "kb_col1_pq1",
638
+					      "kb_col6_pq6",
639
+					      "kb_col7_pq7",
640
+					      "kb_row5_pr5",
641
+					      "kb_row6_pr6",
642
+					      "kb_row7_pr7",
643
+					      "kb_row9_ps1";
644
+				nvidia,function = "kbc";
645
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
646
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
647
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
648
+			};
649
+			kb-row0-pr0 {
650
+				nvidia,pins = "kb_row0_pr0",
651
+					      "kb_row1_pr1",
652
+					      "kb_row2_pr2",
653
+					      "kb_row3_pr3";
654
+				nvidia,function = "rsvd3";
655
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
656
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
657
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658
+			};
659
+			lcd-pwr2-pc6 {
660
+				nvidia,pins = "lcd_pwr2_pc6";
661
+				nvidia,function = "hdcp";
662
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
663
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
664
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
179665 			};
180666 
181667 			/* Power I2C (On-module) */
182
-			pwr_i2c_scl_pz6 {
668
+			pwr-i2c-scl-pz6 {
183669 				nvidia,pins = "pwr_i2c_scl_pz6",
184670 					      "pwr_i2c_sda_pz7";
185671 				nvidia,function = "i2cpwr";
186672 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187673 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
188674 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189
-				nvidia,lock = <TEGRA_PIN_DISABLE>;
190675 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
191676 			};
192677 
....@@ -195,15 +680,15 @@
195680 			 * temperature sensor therefore requires disabling for
196681 			 * now
197682 			 */
198
-			lcd_dc1_pd2 {
683
+			lcd-dc1-pd2 {
199684 				nvidia,pins = "lcd_dc1_pd2";
200685 				nvidia,function = "rsvd3";
201
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
203
-				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
686
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
687
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
688
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
204689 			};
205690 
206
-			/* TOUCH_PEN_INT# */
691
+			/* TOUCH_PEN_INT# (On-module) */
207692 			pv0 {
208693 				nvidia,pins = "pv0";
209694 				nvidia,function = "rsvd1";
....@@ -214,13 +699,21 @@
214699 		};
215700 	};
216701 
217
-	hdmiddc: i2c@7000c700 {
702
+	serial@70006040 {
703
+		compatible = "nvidia,tegra30-hsuart";
704
+	};
705
+
706
+	serial@70006300 {
707
+		compatible = "nvidia,tegra30-hsuart";
708
+	};
709
+
710
+	hdmi_ddc: i2c@7000c700 {
218711 		clock-frequency = <10000>;
219712 	};
220713 
221714 	/*
222715 	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
223
-	 * touch screen controller
716
+	 * touch screen controller (On-module)
224717 	 */
225718 	i2c@7000d000 {
226719 		status = "okay";
....@@ -230,12 +723,14 @@
230723 		sgtl5000: codec@a {
231724 			compatible = "fsl,sgtl5000";
232725 			reg = <0x0a>;
233
-			VDDA-supply = <&sys_3v3_reg>;
234
-			VDDIO-supply = <&sys_3v3_reg>;
726
+			#sound-dai-cells = <0>;
727
+			VDDA-supply = <&reg_module_3v3_audio>;
728
+			VDDD-supply = <&reg_1v8_vio>;
729
+			VDDIO-supply = <&reg_module_3v3>;
235730 			clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
236731 		};
237732 
238
-		pmic: tps65911@2d {
733
+		pmic: pmic@2d {
239734 			compatible = "ti,tps65911";
240735 			reg = <0x2d>;
241736 
....@@ -248,19 +743,18 @@
248743 			#gpio-cells = <2>;
249744 			gpio-controller;
250745 
251
-			vcc1-supply = <&sys_3v3_reg>;
252
-			vcc2-supply = <&sys_3v3_reg>;
253
-			vcc3-supply = <&vio_reg>;
254
-			vcc4-supply = <&sys_3v3_reg>;
255
-			vcc5-supply = <&sys_3v3_reg>;
256
-			vcc6-supply = <&vio_reg>;
257
-			vcc7-supply = <&charge_pump_5v0_reg>;
258
-			vccio-supply = <&sys_3v3_reg>;
746
+			vcc1-supply = <&reg_module_3v3>;
747
+			vcc2-supply = <&reg_module_3v3>;
748
+			vcc3-supply = <&reg_1v8_vio>;
749
+			vcc4-supply = <&reg_module_3v3>;
750
+			vcc5-supply = <&reg_module_3v3>;
751
+			vcc6-supply = <&reg_1v8_vio>;
752
+			vcc7-supply = <&reg_5v0_charge_pump>;
753
+			vccio-supply = <&reg_module_3v3>;
259754 
260755 			regulators {
261
-				/* SW1: +V1.35_VDDIO_DDR */
262756 				vdd1_reg: vdd1 {
263
-					regulator-name = "vddio_ddr_1v35";
757
+					regulator-name = "+V1.35_VDDIO_DDR";
264758 					regulator-min-microvolt = <1350000>;
265759 					regulator-max-microvolt = <1350000>;
266760 					regulator-always-on;
....@@ -268,17 +762,15 @@
268762 
269763 				/* SW2: unused */
270764 
271
-				/* SW CTRL: +V1.0_VDD_CPU */
272765 				vddctrl_reg: vddctrl {
273
-					regulator-name = "vdd_cpu,vdd_sys";
766
+					regulator-name = "+V1.0_VDD_CPU";
274767 					regulator-min-microvolt = <1150000>;
275768 					regulator-max-microvolt = <1150000>;
276769 					regulator-always-on;
277770 				};
278771 
279
-				/* SWIO: +V1.8 */
280
-				vio_reg: vio {
281
-					regulator-name = "vdd_1v8_gen";
772
+				reg_1v8_vio: vio {
773
+					regulator-name = "+V1.8";
282774 					regulator-min-microvolt = <1800000>;
283775 					regulator-max-microvolt = <1800000>;
284776 					regulator-always-on;
....@@ -289,10 +781,10 @@
289781 				/*
290782 				 * EN_+V3.3 switching via FET:
291783 				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
292
-				 * see also 3v3 fixed supply
784
+				 * see also +V3.3 fixed supply
293785 				 */
294786 				ldo2_reg: ldo2 {
295
-					regulator-name = "en_3v3";
787
+					regulator-name = "EN_+V3.3";
296788 					regulator-min-microvolt = <3300000>;
297789 					regulator-max-microvolt = <3300000>;
298790 					regulator-always-on;
....@@ -300,9 +792,8 @@
300792 
301793 				/* LDO3: unused */
302794 
303
-				/* +V1.2_VDD_RTC */
304795 				ldo4_reg: ldo4 {
305
-					regulator-name = "vdd_rtc";
796
+					regulator-name = "+V1.2_VDD_RTC";
306797 					regulator-min-microvolt = <1200000>;
307798 					regulator-max-microvolt = <1200000>;
308799 					regulator-always-on;
....@@ -310,10 +801,10 @@
310801 
311802 				/*
312803 				 * +V2.8_AVDD_VDAC:
313
-				 * only required for analog RGB
804
+				 * only required for (unsupported) analog RGB
314805 				 */
315806 				ldo5_reg: ldo5 {
316
-					regulator-name = "avdd_vdac";
807
+					regulator-name = "+V2.8_AVDD_VDAC";
317808 					regulator-min-microvolt = <2800000>;
318809 					regulator-max-microvolt = <2800000>;
319810 					regulator-always-on;
....@@ -325,22 +816,20 @@
325816 				 * granularity
326817 				 */
327818 				ldo6_reg: ldo6 {
328
-					regulator-name = "avdd_plle";
819
+					regulator-name = "+V1.05_AVDD_PLLE";
329820 					regulator-min-microvolt = <1100000>;
330821 					regulator-max-microvolt = <1100000>;
331822 				};
332823 
333
-				/* +V1.2_AVDD_PLL */
334824 				ldo7_reg: ldo7 {
335
-					regulator-name = "avdd_pll";
825
+					regulator-name = "+V1.2_AVDD_PLL";
336826 					regulator-min-microvolt = <1200000>;
337827 					regulator-max-microvolt = <1200000>;
338828 					regulator-always-on;
339829 				};
340830 
341
-				/* +V1.0_VDD_DDR_HS */
342831 				ldo8_reg: ldo8 {
343
-					regulator-name = "vdd_ddr_hs";
832
+					regulator-name = "+V1.0_VDD_DDR_HS";
344833 					regulator-min-microvolt = <1000000>;
345834 					regulator-max-microvolt = <1000000>;
346835 					regulator-always-on;
....@@ -349,20 +838,26 @@
349838 		};
350839 
351840 		/* STMPE811 touch screen controller */
352
-		stmpe811@41 {
841
+		touchscreen@41 {
353842 			compatible = "st,stmpe811";
354843 			reg = <0x41>;
355
-			interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
356
-			interrupt-parent = <&gpio>;
844
+			irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
357845 			interrupt-controller;
358846 			id = <0>;
359847 			blocks = <0x5>;
360848 			irq-trigger = <0x1>;
849
+			/* 3.25 MHz ADC clock speed */
850
+			st,adc-freq = <1>;
851
+			/* 12-bit ADC */
852
+			st,mod-12b = <1>;
853
+			/* internal ADC reference */
854
+			st,ref-sel = <0>;
855
+			/* ADC converstion time: 80 clocks */
856
+			st,sample-time = <4>;
857
+			/* forbid to use ADC channels 3-0 (touch) */
361858 
362859 			stmpe_touchscreen {
363860 				compatible = "st,stmpe-ts";
364
-				/* 3.25 MHz ADC clock speed */
365
-				st,adc-freq = <1>;
366861 				/* 8 sample average control */
367862 				st,ave-ctrl = <3>;
368863 				/* 7 length fractional part in z */
....@@ -372,22 +867,21 @@
372867 				 * current limit value
373868 				 */
374869 				st,i-drive = <1>;
375
-				/* 12-bit ADC */
376
-				st,mod-12b = <1>;
377
-				/* internal ADC reference */
378
-				st,ref-sel = <0>;
379
-				/* ADC converstion time: 80 clocks */
380
-				st,sample-time = <4>;
381870 				/* 1 ms panel driver settling time */
382871 				st,settling = <3>;
383872 				/* 5 ms touch detect interrupt delay */
384873 				st,touch-det-delay = <5>;
385874 			};
875
+
876
+			stmpe_adc {
877
+				compatible = "st,stmpe-adc";
878
+				st,norequest-mask = <0x0F>;
879
+			};
386880 		};
387881 
388882 		/*
389883 		 * LM95245 temperature sensor
390
-		 * Note: OVERT_N directly connected to PMIC PWRDN
884
+		 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
391885 		 */
392886 		temp-sensor@4c {
393887 			compatible = "national,lm95245";
....@@ -395,7 +889,7 @@
395889 		};
396890 
397891 		/* SW: +V1.2_VDD_CORE */
398
-		tps62362@60 {
892
+		regulator@60 {
399893 			compatible = "ti,tps62362";
400894 			reg = <0x60>;
401895 
....@@ -419,6 +913,18 @@
419913 		nvidia,core-pwr-off-time = <0>;
420914 		nvidia,core-power-req-active-high;
421915 		nvidia,sys-clock-req-active-high;
916
+
917
+		/* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
918
+		i2c-thermtrip {
919
+			nvidia,i2c-controller-id = <4>;
920
+			nvidia,bus-addr = <0x2d>;
921
+			nvidia,reg-addr = <0x3f>;
922
+			nvidia,reg-data = <0x1>;
923
+		};
924
+	};
925
+
926
+	hda@70030000 {
927
+		status = "okay";
422928 	};
423929 
424930 	ahub@70080000 {
....@@ -428,79 +934,89 @@
428934 	};
429935 
430936 	/* eMMC */
431
-	sdhci@78000600 {
937
+	mmc@78000600 {
432938 		status = "okay";
433939 		bus-width = <8>;
434940 		non-removable;
941
+		vmmc-supply = <&reg_module_3v3>; /* VCC */
942
+		vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
943
+		mmc-ddr-1_8v;
435944 	};
436945 
437
-	/* EHCI instance 1: USB2_DP/N -> AX88772B */
946
+	/* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
438947 	usb@7d004000 {
439948 		status = "okay";
949
+		#address-cells = <1>;
950
+		#size-cells = <0>;
951
+
952
+		asix@1 {
953
+			reg = <1>;
954
+			local-mac-address = [00 00 00 00 00 00];
955
+		};
440956 	};
441957 
442958 	usb-phy@7d004000 {
443959 		status = "okay";
444
-		nvidia,is-wired = <1>;
960
+		vbus-supply = <&reg_lan_v_bus>;
445961 	};
446962 
447
-	clocks {
448
-		compatible = "simple-bus";
449
-		#address-cells = <1>;
450
-		#size-cells = <0>;
451
-
452
-		clk32k_in: clk@0 {
453
-			compatible = "fixed-clock";
454
-			reg = <0>;
455
-			#clock-cells = <0>;
456
-			clock-frequency = <32768>;
457
-		};
963
+	clk32k_in: xtal1 {
964
+		compatible = "fixed-clock";
965
+		#clock-cells = <0>;
966
+		clock-frequency = <32768>;
458967 	};
459968 
460
-	regulators {
461
-		compatible = "simple-bus";
462
-		#address-cells = <1>;
463
-		#size-cells = <0>;
969
+	reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
970
+		compatible = "regulator-fixed";
971
+		regulator-name = "+V1.8_AVDD_HDMI_PLL";
972
+		regulator-min-microvolt = <1800000>;
973
+		regulator-max-microvolt = <1800000>;
974
+		enable-active-high;
975
+		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
976
+		vin-supply = <&reg_1v8_vio>;
977
+	};
464978 
465
-		avdd_hdmi_pll_1v8_reg: regulator@100 {
466
-			compatible = "regulator-fixed";
467
-			reg = <100>;
468
-			regulator-name = "+V1.8_AVDD_HDMI_PLL";
469
-			regulator-min-microvolt = <1800000>;
470
-			regulator-max-microvolt = <1800000>;
471
-			enable-active-high;
472
-			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
473
-			vin-supply = <&vio_reg>;
474
-		};
979
+	reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
980
+		compatible = "regulator-fixed";
981
+		regulator-name = "+V3.3_AVDD_HDMI";
982
+		regulator-min-microvolt = <3300000>;
983
+		regulator-max-microvolt = <3300000>;
984
+		enable-active-high;
985
+		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
986
+		vin-supply = <&reg_module_3v3>;
987
+	};
475988 
476
-		sys_3v3_reg: regulator@101 {
477
-			compatible = "regulator-fixed";
478
-			reg = <101>;
479
-			regulator-name = "3v3";
480
-			regulator-min-microvolt = <3300000>;
481
-			regulator-max-microvolt = <3300000>;
482
-			regulator-always-on;
483
-		};
989
+	reg_5v0_charge_pump: regulator-5v0-charge-pump {
990
+		compatible = "regulator-fixed";
991
+		regulator-name = "+V5.0";
992
+		regulator-min-microvolt = <5000000>;
993
+		regulator-max-microvolt = <5000000>;
994
+		regulator-always-on;
995
+	};
484996 
485
-		avdd_hdmi_3v3_reg: regulator@102 {
486
-			compatible = "regulator-fixed";
487
-			reg = <102>;
488
-			regulator-name = "+V3.3_AVDD_HDMI";
489
-			regulator-min-microvolt = <3300000>;
490
-			regulator-max-microvolt = <3300000>;
491
-			enable-active-high;
492
-			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
493
-			vin-supply = <&sys_3v3_reg>;
494
-		};
997
+	reg_lan_v_bus: regulator-lan-v-bus {
998
+		compatible = "regulator-fixed";
999
+		regulator-name = "LAN_V_BUS";
1000
+		regulator-min-microvolt = <5000000>;
1001
+		regulator-max-microvolt = <5000000>;
1002
+		enable-active-high;
1003
+		gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
1004
+	};
4951005 
496
-		charge_pump_5v0_reg: regulator@103 {
497
-			compatible = "regulator-fixed";
498
-			reg = <103>;
499
-			regulator-name = "5v0";
500
-			regulator-min-microvolt = <5000000>;
501
-			regulator-max-microvolt = <5000000>;
502
-			regulator-always-on;
503
-		};
1006
+	reg_module_3v3: regulator-module-3v3 {
1007
+		compatible = "regulator-fixed";
1008
+		regulator-name = "+V3.3";
1009
+		regulator-min-microvolt = <3300000>;
1010
+		regulator-max-microvolt = <3300000>;
1011
+		regulator-always-on;
1012
+	};
1013
+
1014
+	reg_module_3v3_audio: regulator-module-3v3-audio {
1015
+		compatible = "regulator-fixed";
1016
+		regulator-name = "+V3.3_AUDIO_AVDD_S";
1017
+		regulator-min-microvolt = <3300000>;
1018
+		regulator-max-microvolt = <3300000>;
1019
+		regulator-always-on;
5041020 	};
5051021 
5061022 	sound {
....@@ -515,7 +1031,22 @@
5151031 		nvidia,audio-codec = <&sgtl5000>;
5161032 		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
5171033 			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
518
-			 <&tegra_car TEGRA30_CLK_EXTERN1>;
1034
+			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
5191035 		clock-names = "pll_a", "pll_a_out0", "mclk";
1036
+
1037
+		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1038
+				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1039
+
1040
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1041
+					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1042
+	};
1043
+};
1044
+
1045
+&gpio {
1046
+	lan-reset-n {
1047
+		gpio-hog;
1048
+		gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
1049
+		output-high;
1050
+		line-name = "LAN_RESET#";
5201051 	};
5211052 };