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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/arch/arm/boot/dts/sun5i.dtsi
..
..
@@ -42,14 +42,14 @@
42
42
  *     OTHER DEALINGS IN THE SOFTWARE.
43
43
  */
44
44
 
45
-#include "skeleton.dtsi"
46
-
47
45
 #include <dt-bindings/clock/sun5i-ccu.h>
48
46
 #include <dt-bindings/dma/sun4i-a10.h>
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 #include <dt-bindings/reset/sun5i-ccu.h>
50
48
 
51
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 / {
52
50
 	interrupt-parent = <&intc>;
51
+	#address-cells = <1>;
52
+	#size-cells = <1>;
53
53
 
54
54
 	cpus {
55
55
 		#address-cells = <1>;
..
..
@@ -68,7 +68,7 @@
68
68
 		#size-cells = <1>;
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69
 		ranges;
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70
 
71
-		framebuffer@0 {
71
+		framebuffer-lcd0 {
72
72
 			compatible = "allwinner,simple-framebuffer",
73
73
 				     "simple-framebuffer";
74
74
 			allwinner,pipeline = "de_be0-lcd0";
..
..
@@ -77,7 +77,7 @@
77
77
 			status = "disabled";
78
78
 		};
79
79
 
80
-		framebuffer@1 {
80
+		framebuffer-lcd0-tve0 {
81
81
 			compatible = "allwinner,simple-framebuffer",
82
82
 				     "simple-framebuffer";
83
83
 			allwinner,pipeline = "de_be0-lcd0-tve0";
..
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@@ -93,14 +93,14 @@
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93
 		#size-cells = <1>;
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94
 		ranges;
95
95
 
96
-		osc24M: clk@1c20050 {
96
+		osc24M: clk-24M {
97
97
 			#clock-cells = <0>;
98
98
 			compatible = "fixed-clock";
99
99
 			clock-frequency = <24000000>;
100
100
 			clock-output-names = "osc24M";
101
101
 		};
102
102
 
103
-		osc32k: clk@0 {
103
+		osc32k: clk-32k {
104
104
 			#clock-cells = <0>;
105
105
 			compatible = "fixed-clock";
106
106
 			clock-frequency = <32768>;
..
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@@ -108,10 +108,26 @@
108
108
 		};
109
109
 	};
110
110
 
111
-	soc@1c00000 {
111
+	reserved-memory {
112
+		#address-cells = <1>;
113
+		#size-cells = <1>;
114
+		ranges;
115
+
116
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
117
+		default-pool {
118
+			compatible = "shared-dma-pool";
119
+			size = <0x6000000>;
120
+			alloc-ranges = <0x40000000 0x10000000>;
121
+			reusable;
122
+			linux,cma-default;
123
+		};
124
+	};
125
+
126
+	soc {
112
127
 		compatible = "simple-bus";
113
128
 		#address-cells = <1>;
114
129
 		#size-cells = <1>;
130
+		dma-ranges;
115
131
 		ranges;
116
132
 
117
133
 		system-control@1c00000 {
..
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@@ -166,6 +182,16 @@
166
182
 			};
167
183
 		};
168
184
 
185
+		mbus: dram-controller@1c01000 {
186
+			compatible = "allwinner,sun5i-a13-mbus";
187
+			reg = <0x01c01000 0x1000>;
188
+			clocks = <&ccu CLK_MBUS>;
189
+			#address-cells = <1>;
190
+			#size-cells = <1>;
191
+			dma-ranges = <0x00000000 0x40000000 0x20000000>;
192
+			#interconnect-cells = <1>;
193
+		};
194
+
169
195
 		dma: dma-controller@1c02000 {
170
196
 			compatible = "allwinner,sun4i-a10-dma";
171
197
 			reg = <0x01c02000 0x1000>;
..
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@@ -174,7 +200,7 @@
174
200
 			#dma-cells = <2>;
175
201
 		};
176
202
 
177
-		nfc: nand@1c03000 {
203
+		nfc: nand-controller@1c03000 {
178
204
 			compatible = "allwinner,sun4i-a10-nand";
179
205
 			reg = <0x01c03000 0x1000>;
180
206
 			interrupts = <37>;
..
..
@@ -223,11 +249,8 @@
223
249
 			status = "disabled";
224
250
 
225
251
 			port {
226
-				#address-cells = <1>;
227
-				#size-cells = <0>;
228
252
 
229
-				tve0_in_tcon0: endpoint@0 {
230
-					reg = <0>;
253
+				tve0_in_tcon0: endpoint {
231
254
 					remote-endpoint = <&tcon0_out_tve0>;
232
255
 				};
233
256
 			};
..
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@@ -254,6 +277,7 @@
254
277
 			compatible = "allwinner,sun5i-a13-tcon";
255
278
 			reg = <0x01c0c000 0x1000>;
256
279
 			interrupts = <44>;
280
+			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
257
281
 			resets = <&ccu RST_LCD>;
258
282
 			reset-names = "lcd";
259
283
 			clocks = <&ccu CLK_AHB_LCD>,
..
..
@@ -263,6 +287,7 @@
263
287
 				      "tcon-ch0",
264
288
 				      "tcon-ch1";
265
289
 			clock-output-names = "tcon-pixel-clock";
290
+			#clock-cells = <0>;
266
291
 			status = "disabled";
267
292
 
268
293
 			ports {
..
..
@@ -270,12 +295,9 @@
270
295
 				#size-cells = <0>;
271
296
 
272
297
 				tcon0_in: port@0 {
273
-					#address-cells = <1>;
274
-					#size-cells = <0>;
275
298
 					reg = <0>;
276
299
 
277
-					tcon0_in_be0: endpoint@0 {
278
-						reg = <0>;
300
+					tcon0_in_be0: endpoint {
279
301
 						remote-endpoint = <&be0_out_tcon0>;
280
302
 					};
281
303
 				};
..
..
@@ -294,12 +316,25 @@
294
316
 			};
295
317
 		};
296
318
 
319
+		video-codec@1c0e000 {
320
+			compatible = "allwinner,sun5i-a13-video-engine";
321
+			reg = <0x01c0e000 0x1000>;
322
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
323
+				 <&ccu CLK_DRAM_VE>;
324
+			clock-names = "ahb", "mod", "ram";
325
+			resets = <&ccu RST_VE>;
326
+			interrupts = <53>;
327
+			allwinner,sram = <&ve_sram 1>;
328
+		};
329
+
297
330
 		mmc0: mmc@1c0f000 {
298
331
 			compatible = "allwinner,sun5i-a13-mmc";
299
332
 			reg = <0x01c0f000 0x1000>;
300
333
 			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
301
334
 			clock-names = "ahb", "mmc";
302
335
 			interrupts = <32>;
336
+			pinctrl-names = "default";
337
+			pinctrl-0 = <&mmc0_pins>;
303
338
 			status = "disabled";
304
339
 			#address-cells = <1>;
305
340
 			#size-cells = <0>;
..
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@@ -337,13 +372,14 @@
337
372
 			phy-names = "usb";
338
373
 			extcon = <&usbphy 0>;
339
374
 			allwinner,sram = <&otg_sram 1>;
375
+			dr_mode = "otg";
340
376
 			status = "disabled";
341
377
 		};
342
378
 
343
379
 		usbphy: phy@1c13400 {
344
380
 			#phy-cells = <1>;
345
381
 			compatible = "allwinner,sun5i-a13-usb-phy";
346
-			reg = <0x01c13400 0x10 0x01c14800 0x4>;
382
+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
347
383
 			reg-names = "phy_ctrl", "pmu1";
348
384
 			clocks = <&ccu CLK_USB_PHY0>;
349
385
 			clock-names = "usb_phy";
..
..
@@ -420,7 +456,7 @@
420
456
 			#interrupt-cells = <3>;
421
457
 			#gpio-cells = <3>;
422
458
 
423
-			emac_pins_a: emac0@0 {
459
+			emac_pd_pins: emac-pd-pins {
424
460
 				pins = "PD6", "PD7", "PD10",
425
461
 				       "PD11", "PD12", "PD13", "PD14",
426
462
 				       "PD15", "PD18", "PD19", "PD20",
..
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@@ -429,27 +465,27 @@
429
465
 				function = "emac";
430
466
 			};
431
467
 
432
-			i2c0_pins_a: i2c0@0 {
468
+			i2c0_pins: i2c0-pins {
433
469
 				pins = "PB0", "PB1";
434
470
 				function = "i2c0";
435
471
 			};
436
472
 
437
-			i2c1_pins_a: i2c1@0 {
473
+			i2c1_pins: i2c1-pins {
438
474
 				pins = "PB15", "PB16";
439
475
 				function = "i2c1";
440
476
 			};
441
477
 
442
-			i2c2_pins_a: i2c2@0 {
478
+			i2c2_pins: i2c2-pins {
443
479
 				pins = "PB17", "PB18";
444
480
 				function = "i2c2";
445
481
 			};
446
482
 
447
-			ir0_rx_pins_a: ir0@0 {
483
+			ir0_rx_pin: ir0-rx-pin {
448
484
 				pins = "PB4";
449
485
 				function = "ir0";
450
486
 			};
451
487
 
452
-			lcd_rgb565_pins: lcd_rgb565@0 {
488
+			lcd_rgb565_pins: lcd-rgb565-pins {
453
489
 				pins = "PD3", "PD4", "PD5", "PD6", "PD7",
454
490
 						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
455
491
 						 "PD19", "PD20", "PD21", "PD22", "PD23",
..
..
@@ -457,7 +493,7 @@
457
493
 				function = "lcd0";
458
494
 			};
459
495
 
460
-			lcd_rgb666_pins: lcd_rgb666@0 {
496
+			lcd_rgb666_pins: lcd-rgb666-pins {
461
497
 				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
462
498
 				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
463
499
 				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
..
..
@@ -465,7 +501,7 @@
465
501
 				function = "lcd0";
466
502
 			};
467
503
 
468
-			mmc0_pins_a: mmc0@0 {
504
+			mmc0_pins: mmc0-pins {
469
505
 				pins = "PF0", "PF1", "PF2", "PF3",
470
506
 				       "PF4", "PF5";
471
507
 				function = "mmc0";
..
..
@@ -473,7 +509,15 @@
473
509
 				bias-pull-up;
474
510
 			};
475
511
 
476
-			mmc2_pins_a: mmc2@0 {
512
+			mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
513
+				pins = "PC6", "PC7", "PC8", "PC9",
514
+				       "PC10", "PC11";
515
+				function = "mmc2";
516
+				drive-strength = <30>;
517
+				bias-pull-up;
518
+			};
519
+
520
+			mmc2_8bit_pins: mmc2-8bit-pins {
477
521
 				pins = "PC6", "PC7", "PC8", "PC9",
478
522
 				       "PC10", "PC11", "PC12", "PC13",
479
523
 				       "PC14", "PC15";
..
..
@@ -482,15 +526,7 @@
482
526
 				bias-pull-up;
483
527
 			};
484
528
 
485
-			mmc2_4bit_pins_a: mmc2-4bit@0 {
486
-				pins = "PC6", "PC7", "PC8", "PC9",
487
-				       "PC10", "PC11";
488
-				function = "mmc2";
489
-				drive-strength = <30>;
490
-				bias-pull-up;
491
-			};
492
-
493
-			nand_pins_a: nand-base0@0 {
529
+			nand_pins: nand-pins {
494
530
 				pins = "PC0", "PC1", "PC2",
495
531
 				       "PC5", "PC8", "PC9", "PC10",
496
532
 				       "PC11", "PC12", "PC13", "PC14",
..
..
@@ -498,72 +534,79 @@
498
534
 				function = "nand0";
499
535
 			};
500
536
 
501
-			nand_cs0_pins_a: nand-cs@0 {
537
+			nand_cs0_pin: nand-cs0-pin {
502
538
 				pins = "PC4";
503
539
 				function = "nand0";
504
540
 			};
505
541
 
506
-			nand_rb0_pins_a: nand-rb@0 {
542
+			nand_rb0_pin: nand-rb0-pin {
507
543
 				pins = "PC6";
508
544
 				function = "nand0";
509
545
 			};
510
546
 
511
-			spi2_pins_a: spi2@0 {
547
+			pwm0_pin: pwm0-pin {
548
+				pins = "PB2";
549
+				function = "pwm";
550
+			};
551
+
552
+			spi2_pe_pins: spi2-pe-pins {
512
553
 				pins = "PE1", "PE2", "PE3";
513
554
 				function = "spi2";
514
555
 			};
515
556
 
516
-			spi2_cs0_pins_a: spi2-cs0@0 {
557
+			spi2_cs0_pe_pin: spi2-cs0-pe-pin {
517
558
 				pins = "PE0";
518
559
 				function = "spi2";
519
560
 			};
520
561
 
521
-			uart1_pins_a: uart1@0 {
562
+			uart1_pe_pins: uart1-pe-pins {
522
563
 				pins = "PE10", "PE11";
523
564
 				function = "uart1";
524
565
 			};
525
566
 
526
-			uart1_pins_b: uart1@1 {
567
+			uart1_pg_pins: uart1-pg-pins {
527
568
 				pins = "PG3", "PG4";
528
569
 				function = "uart1";
529
570
 			};
530
571
 
531
-			uart2_pins_a: uart2@0 {
572
+			uart2_pd_pins: uart2-pd-pins {
532
573
 				pins = "PD2", "PD3";
533
574
 				function = "uart2";
534
575
 			};
535
576
 
536
-			uart2_cts_rts_pins_a: uart2-cts-rts@0 {
577
+			uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
537
578
 				pins = "PD4", "PD5";
538
579
 				function = "uart2";
539
580
 			};
540
581
 
541
-			uart3_pins_a: uart3@0 {
582
+			uart3_pg_pins: uart3-pg-pins {
542
583
 				pins = "PG9", "PG10";
543
584
 				function = "uart3";
544
585
 			};
545
586
 
546
-			uart3_cts_rts_pins_a: uart3-cts-rts@0 {
587
+			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
547
588
 				pins = "PG11", "PG12";
548
589
 				function = "uart3";
549
-			};
550
-
551
-			pwm0_pins: pwm0 {
552
-				pins = "PB2";
553
-				function = "pwm";
554
590
 			};
555
591
 		};
556
592
 
557
593
 		timer@1c20c00 {
558
594
 			compatible = "allwinner,sun4i-a10-timer";
559
595
 			reg = <0x01c20c00 0x90>;
560
-			interrupts = <22>;
596
+			interrupts = <22>,
597
+				     <23>,
598
+				     <24>,
599
+				     <25>,
600
+				     <67>,
601
+				     <68>;
561
602
 			clocks = <&ccu CLK_HOSC>;
562
603
 		};
563
604
 
564
605
 		wdt: watchdog@1c20c90 {
565
606
 			compatible = "allwinner,sun4i-a10-wdt";
566
607
 			reg = <0x01c20c90 0x10>;
608
+			interrupts = <24>;
609
+			clocks = <&osc24M>;
567
610
 		};
568
611
 
569
612
 		ir0: ir@1c21800 {
..
..
@@ -652,6 +695,8 @@
652
695
 			reg = <0x01c2ac00 0x400>;
653
696
 			interrupts = <7>;
654
697
 			clocks = <&ccu CLK_APB1_I2C0>;
698
+			pinctrl-names = "default";
699
+			pinctrl-0 = <&i2c0_pins>;
655
700
 			status = "disabled";
656
701
 			#address-cells = <1>;
657
702
 			#size-cells = <0>;
..
..
@@ -662,6 +707,8 @@
662
707
 			reg = <0x01c2b000 0x400>;
663
708
 			interrupts = <8>;
664
709
 			clocks = <&ccu CLK_APB1_I2C1>;
710
+			pinctrl-names = "default";
711
+			pinctrl-0 = <&i2c1_pins>;
665
712
 			status = "disabled";
666
713
 			#address-cells = <1>;
667
714
 			#size-cells = <0>;
..
..
@@ -672,6 +719,8 @@
672
719
 			reg = <0x01c2b400 0x400>;
673
720
 			interrupts = <9>;
674
721
 			clocks = <&ccu CLK_APB1_I2C2>;
722
+			pinctrl-names = "default";
723
+			pinctrl-0 = <&i2c2_pins>;
675
724
 			status = "disabled";
676
725
 			#address-cells = <1>;
677
726
 			#size-cells = <0>;
..
..
@@ -693,6 +742,8 @@
693
742
 			clock-names = "ahb", "mod",
694
743
 				      "ram";
695
744
 			resets = <&ccu RST_DE_FE>;
745
+			interconnects = <&mbus 19>;
746
+			interconnect-names = "dma-mem";
696
747
 			status = "disabled";
697
748
 
698
749
 			ports {
..
..
@@ -700,12 +751,9 @@
700
751
 				#size-cells = <0>;
701
752
 
702
753
 				fe0_out: port@1 {
703
-					#address-cells = <1>;
704
-					#size-cells = <0>;
705
754
 					reg = <1>;
706
755
 
707
-					fe0_out_be0: endpoint@0 {
708
-						reg = <0>;
756
+					fe0_out_be0: endpoint {
709
757
 						remote-endpoint = <&be0_in_fe0>;
710
758
 					};
711
759
 				};
..
..
@@ -721,33 +769,26 @@
721
769
 			clock-names = "ahb", "mod",
722
770
 				      "ram";
723
771
 			resets = <&ccu RST_DE_BE>;
772
+			interconnects = <&mbus 18>;
773
+			interconnect-names = "dma-mem";
724
774
 			status = "disabled";
725
-
726
-			assigned-clocks = <&ccu CLK_DE_BE>;
727
-			assigned-clock-rates = <300000000>;
728
775
 
729
776
 			ports {
730
777
 				#address-cells = <1>;
731
778
 				#size-cells = <0>;
732
779
 
733
780
 				be0_in: port@0 {
734
-					#address-cells = <1>;
735
-					#size-cells = <0>;
736
781
 					reg = <0>;
737
782
 
738
-					be0_in_fe0: endpoint@0 {
739
-						reg = <0>;
783
+					be0_in_fe0: endpoint {
740
784
 						remote-endpoint = <&fe0_out_be0>;
741
785
 					};
742
786
 				};
743
787
 
744
788
 				be0_out: port@1 {
745
-					#address-cells = <1>;
746
-					#size-cells = <0>;
747
789
 					reg = <1>;
748
790
 
749
-					be0_out_tcon0: endpoint@0 {
750
-						reg = <0>;
791
+					be0_out_tcon0: endpoint {
751
792
 						remote-endpoint = <&tcon0_in_be0>;
752
793
 					};
753
794
 				};