~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,13 +1,17 @@
1	1	// SPDX-License-Identifier: GPL-2.0
2	2	/dts-v1/;
3	3
4		-#include "skeleton.dtsi"
	4	+#include <dt-bindings/interrupt-controller/arm-gic.h>
5	5	#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6	6	#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
	7	+#include <dt-bindings/gpio/gpio.h>
	8	+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
7	9	#include <dt-bindings/soc/qcom,gsbi.h>
8	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
9	11
10	12	/ {
	13	+ #address-cells = <1>;
	14	+ #size-cells = <1>;
11	15	model = "Qualcomm IPQ8064";
12	16	compatible = "qcom,ipq8064";
13	17	interrupt-parent = <&intc>;
..	..	@@ -40,6 +44,11 @@
40	44	compatible = "cache";
41	45	cache-level = <2>;
42	46	};
	47	+ };
	48	+
	49	+ memory {
	50	+ device_type = "memory";
	51	+ reg = <0x0 0x0>;
43	52	};
44	53
45	54	cpu-pmu {
..	..	@@ -84,6 +93,12 @@
84	93	};
85	94	};
86	95
	96	+ firmware {
	97	+ scm {
	98	+ compatible = "qcom,scm-ipq806x", "qcom,scm";
	99	+ };
	100	+ };
	101	+
87	102	soc: soc {
88	103	#address-cells = <1>;
89	104	#size-cells = <1>;
..	..	@@ -110,10 +125,66 @@
110	125	reg = <0x800000 0x4000>;
111	126
112	127	gpio-controller;
	128	+ gpio-ranges = <&qcom_pinmux 0 0 69>;
113	129	#gpio-cells = <2>;
114	130	interrupt-controller;
115	131	#interrupt-cells = <2>;
116	132	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	133	+
	134	+ pcie0_pins: pcie0_pinmux {
	135	+ mux {
	136	+ pins = "gpio3";
	137	+ function = "pcie1_rst";
	138	+ drive-strength = <12>;
	139	+ bias-disable;
	140	+ };
	141	+ };
	142	+
	143	+ pcie1_pins: pcie1_pinmux {
	144	+ mux {
	145	+ pins = "gpio48";
	146	+ function = "pcie2_rst";
	147	+ drive-strength = <12>;
	148	+ bias-disable;
	149	+ };
	150	+ };
	151	+
	152	+ pcie2_pins: pcie2_pinmux {
	153	+ mux {
	154	+ pins = "gpio63";
	155	+ function = "pcie3_rst";
	156	+ drive-strength = <12>;
	157	+ bias-disable;
	158	+ };
	159	+ };
	160	+
	161	+ spi_pins: spi_pins {
	162	+ mux {
	163	+ pins = "gpio18", "gpio19", "gpio21";
	164	+ function = "gsbi5";
	165	+ drive-strength = <10>;
	166	+ bias-none;
	167	+ };
	168	+ };
	169	+
	170	+ leds_pins: leds_pins {
	171	+ mux {
	172	+ pins = "gpio7", "gpio8", "gpio9",
	173	+ "gpio26", "gpio53";
	174	+ function = "gpio";
	175	+ drive-strength = <2>;
	176	+ bias-pull-down;
	177	+ output-low;
	178	+ };
	179	+ };
	180	+
	181	+ buttons_pins: buttons_pins {
	182	+ mux {
	183	+ pins = "gpio54";
	184	+ drive-strength = <2>;
	185	+ bias-pull-up;
	186	+ };
	187	+ };
117	188	};
118	189
119	190	intc: interrupt-controller@2000000 {
..	..	@@ -354,6 +425,13 @@
354	425	qcom,controller-type = "pmic-arbiter";
355	426	};
356	427
	428	+ qfprom: qfprom@700000 {
	429	+ compatible = "qcom,qfprom";
	430	+ reg = <0x00700000 0x1000>;
	431	+ #address-cells = <1>;
	432	+ #size-cells = <1>;
	433	+ };
	434	+
357	435	gcc: clock-controller@900000 {
358	436	compatible = "qcom,gcc-ipq8064";
359	437	reg = <0x00900000 0x4000>;
..	..	@@ -373,5 +451,341 @@
373	451	#reset-cells = <1>;
374	452	};
375	453
	454	+ pcie0: pci@1b500000 {
	455	+ compatible = "qcom,pcie-ipq8064";
	456	+ reg = <0x1b500000 0x1000
	457	+ 0x1b502000 0x80
	458	+ 0x1b600000 0x100
	459	+ 0x0ff00000 0x100000>;
	460	+ reg-names = "dbi", "elbi", "parf", "config";
	461	+ device_type = "pci";
	462	+ linux,pci-domain = <0>;
	463	+ bus-range = <0x00 0xff>;
	464	+ num-lanes = <1>;
	465	+ #address-cells = <3>;
	466	+ #size-cells = <2>;
	467	+
	468	+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
	469	+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
	470	+
	471	+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	472	+ interrupt-names = "msi";
	473	+ #interrupt-cells = <1>;
	474	+ interrupt-map-mask = <0 0 0 0x7>;
	475	+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	476	+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	477	+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	478	+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	479	+
	480	+ clocks = <&gcc PCIE_A_CLK>,
	481	+ <&gcc PCIE_H_CLK>,
	482	+ <&gcc PCIE_PHY_CLK>,
	483	+ <&gcc PCIE_AUX_CLK>,
	484	+ <&gcc PCIE_ALT_REF_CLK>;
	485	+ clock-names = "core", "iface", "phy", "aux", "ref";
	486	+
	487	+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
	488	+ assigned-clock-rates = <100000000>;
	489	+
	490	+ resets = <&gcc PCIE_ACLK_RESET>,
	491	+ <&gcc PCIE_HCLK_RESET>,
	492	+ <&gcc PCIE_POR_RESET>,
	493	+ <&gcc PCIE_PCI_RESET>,
	494	+ <&gcc PCIE_PHY_RESET>,
	495	+ <&gcc PCIE_EXT_RESET>;
	496	+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
	497	+
	498	+ pinctrl-0 = <&pcie0_pins>;
	499	+ pinctrl-names = "default";
	500	+
	501	+ status = "disabled";
	502	+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
	503	+ };
	504	+
	505	+ pcie1: pci@1b700000 {
	506	+ compatible = "qcom,pcie-ipq8064";
	507	+ reg = <0x1b700000 0x1000
	508	+ 0x1b702000 0x80
	509	+ 0x1b800000 0x100
	510	+ 0x31f00000 0x100000>;
	511	+ reg-names = "dbi", "elbi", "parf", "config";
	512	+ device_type = "pci";
	513	+ linux,pci-domain = <1>;
	514	+ bus-range = <0x00 0xff>;
	515	+ num-lanes = <1>;
	516	+ #address-cells = <3>;
	517	+ #size-cells = <2>;
	518	+
	519	+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
	520	+ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
	521	+
	522	+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	523	+ interrupt-names = "msi";
	524	+ #interrupt-cells = <1>;
	525	+ interrupt-map-mask = <0 0 0 0x7>;
	526	+ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	527	+ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	528	+ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	529	+ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	530	+
	531	+ clocks = <&gcc PCIE_1_A_CLK>,
	532	+ <&gcc PCIE_1_H_CLK>,
	533	+ <&gcc PCIE_1_PHY_CLK>,
	534	+ <&gcc PCIE_1_AUX_CLK>,
	535	+ <&gcc PCIE_1_ALT_REF_CLK>;
	536	+ clock-names = "core", "iface", "phy", "aux", "ref";
	537	+
	538	+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
	539	+ assigned-clock-rates = <100000000>;
	540	+
	541	+ resets = <&gcc PCIE_1_ACLK_RESET>,
	542	+ <&gcc PCIE_1_HCLK_RESET>,
	543	+ <&gcc PCIE_1_POR_RESET>,
	544	+ <&gcc PCIE_1_PCI_RESET>,
	545	+ <&gcc PCIE_1_PHY_RESET>,
	546	+ <&gcc PCIE_1_EXT_RESET>;
	547	+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
	548	+
	549	+ pinctrl-0 = <&pcie1_pins>;
	550	+ pinctrl-names = "default";
	551	+
	552	+ status = "disabled";
	553	+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
	554	+ };
	555	+
	556	+ pcie2: pci@1b900000 {
	557	+ compatible = "qcom,pcie-ipq8064";
	558	+ reg = <0x1b900000 0x1000
	559	+ 0x1b902000 0x80
	560	+ 0x1ba00000 0x100
	561	+ 0x35f00000 0x100000>;
	562	+ reg-names = "dbi", "elbi", "parf", "config";
	563	+ device_type = "pci";
	564	+ linux,pci-domain = <2>;
	565	+ bus-range = <0x00 0xff>;
	566	+ num-lanes = <1>;
	567	+ #address-cells = <3>;
	568	+ #size-cells = <2>;
	569	+
	570	+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
	571	+ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
	572	+
	573	+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	574	+ interrupt-names = "msi";
	575	+ #interrupt-cells = <1>;
	576	+ interrupt-map-mask = <0 0 0 0x7>;
	577	+ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	578	+ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	579	+ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	580	+ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	581	+
	582	+ clocks = <&gcc PCIE_2_A_CLK>,
	583	+ <&gcc PCIE_2_H_CLK>,
	584	+ <&gcc PCIE_2_PHY_CLK>,
	585	+ <&gcc PCIE_2_AUX_CLK>,
	586	+ <&gcc PCIE_2_ALT_REF_CLK>;
	587	+ clock-names = "core", "iface", "phy", "aux", "ref";
	588	+
	589	+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
	590	+ assigned-clock-rates = <100000000>;
	591	+
	592	+ resets = <&gcc PCIE_2_ACLK_RESET>,
	593	+ <&gcc PCIE_2_HCLK_RESET>,
	594	+ <&gcc PCIE_2_POR_RESET>,
	595	+ <&gcc PCIE_2_PCI_RESET>,
	596	+ <&gcc PCIE_2_PHY_RESET>,
	597	+ <&gcc PCIE_2_EXT_RESET>;
	598	+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
	599	+
	600	+ pinctrl-0 = <&pcie2_pins>;
	601	+ pinctrl-names = "default";
	602	+
	603	+ status = "disabled";
	604	+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
	605	+ };
	606	+
	607	+ nss_common: syscon@03000000 {
	608	+ compatible = "syscon";
	609	+ reg = <0x03000000 0x0000FFFF>;
	610	+ };
	611	+
	612	+ qsgmii_csr: syscon@1bb00000 {
	613	+ compatible = "syscon";
	614	+ reg = <0x1bb00000 0x000001FF>;
	615	+ };
	616	+
	617	+ stmmac_axi_setup: stmmac-axi-config {
	618	+ snps,wr_osr_lmt = <7>;
	619	+ snps,rd_osr_lmt = <7>;
	620	+ snps,blen = <16 0 0 0 0 0 0>;
	621	+ };
	622	+
	623	+ gmac0: ethernet@37000000 {
	624	+ device_type = "network";
	625	+ compatible = "qcom,ipq806x-gmac";
	626	+ reg = <0x37000000 0x200000>;
	627	+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
	628	+ interrupt-names = "macirq";
	629	+
	630	+ snps,axi-config = <&stmmac_axi_setup>;
	631	+ snps,pbl = <32>;
	632	+ snps,aal = <1>;
	633	+
	634	+ qcom,nss-common = <&nss_common>;
	635	+ qcom,qsgmii-csr = <&qsgmii_csr>;
	636	+
	637	+ clocks = <&gcc GMAC_CORE1_CLK>;
	638	+ clock-names = "stmmaceth";
	639	+
	640	+ resets = <&gcc GMAC_CORE1_RESET>;
	641	+ reset-names = "stmmaceth";
	642	+
	643	+ status = "disabled";
	644	+ };
	645	+
	646	+ gmac1: ethernet@37200000 {
	647	+ device_type = "network";
	648	+ compatible = "qcom,ipq806x-gmac";
	649	+ reg = <0x37200000 0x200000>;
	650	+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
	651	+ interrupt-names = "macirq";
	652	+
	653	+ snps,axi-config = <&stmmac_axi_setup>;
	654	+ snps,pbl = <32>;
	655	+ snps,aal = <1>;
	656	+
	657	+ qcom,nss-common = <&nss_common>;
	658	+ qcom,qsgmii-csr = <&qsgmii_csr>;
	659	+
	660	+ clocks = <&gcc GMAC_CORE2_CLK>;
	661	+ clock-names = "stmmaceth";
	662	+
	663	+ resets = <&gcc GMAC_CORE2_RESET>;
	664	+ reset-names = "stmmaceth";
	665	+
	666	+ status = "disabled";
	667	+ };
	668	+
	669	+ gmac2: ethernet@37400000 {
	670	+ device_type = "network";
	671	+ compatible = "qcom,ipq806x-gmac";
	672	+ reg = <0x37400000 0x200000>;
	673	+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
	674	+ interrupt-names = "macirq";
	675	+
	676	+ snps,axi-config = <&stmmac_axi_setup>;
	677	+ snps,pbl = <32>;
	678	+ snps,aal = <1>;
	679	+
	680	+ qcom,nss-common = <&nss_common>;
	681	+ qcom,qsgmii-csr = <&qsgmii_csr>;
	682	+
	683	+ clocks = <&gcc GMAC_CORE3_CLK>;
	684	+ clock-names = "stmmaceth";
	685	+
	686	+ resets = <&gcc GMAC_CORE3_RESET>;
	687	+ reset-names = "stmmaceth";
	688	+
	689	+ status = "disabled";
	690	+ };
	691	+
	692	+ gmac3: ethernet@37600000 {
	693	+ device_type = "network";
	694	+ compatible = "qcom,ipq806x-gmac";
	695	+ reg = <0x37600000 0x200000>;
	696	+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
	697	+ interrupt-names = "macirq";
	698	+
	699	+ snps,axi-config = <&stmmac_axi_setup>;
	700	+ snps,pbl = <32>;
	701	+ snps,aal = <1>;
	702	+
	703	+ qcom,nss-common = <&nss_common>;
	704	+ qcom,qsgmii-csr = <&qsgmii_csr>;
	705	+
	706	+ clocks = <&gcc GMAC_CORE4_CLK>;
	707	+ clock-names = "stmmaceth";
	708	+
	709	+ resets = <&gcc GMAC_CORE4_RESET>;
	710	+ reset-names = "stmmaceth";
	711	+
	712	+ status = "disabled";
	713	+ };
	714	+
	715	+ vsdcc_fixed: vsdcc-regulator {
	716	+ compatible = "regulator-fixed";
	717	+ regulator-name = "SDCC Power";
	718	+ regulator-min-microvolt = <3300000>;
	719	+ regulator-max-microvolt = <3300000>;
	720	+ regulator-always-on;
	721	+ };
	722	+
	723	+ sdcc1bam:dma@12402000 {
	724	+ compatible = "qcom,bam-v1.3.0";
	725	+ reg = <0x12402000 0x8000>;
	726	+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	727	+ clocks = <&gcc SDC1_H_CLK>;
	728	+ clock-names = "bam_clk";
	729	+ #dma-cells = <1>;
	730	+ qcom,ee = <0>;
	731	+ };
	732	+
	733	+ sdcc3bam:dma@12182000 {
	734	+ compatible = "qcom,bam-v1.3.0";
	735	+ reg = <0x12182000 0x8000>;
	736	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	737	+ clocks = <&gcc SDC3_H_CLK>;
	738	+ clock-names = "bam_clk";
	739	+ #dma-cells = <1>;
	740	+ qcom,ee = <0>;
	741	+ };
	742	+
	743	+ amba {
	744	+ compatible = "simple-bus";
	745	+ #address-cells = <1>;
	746	+ #size-cells = <1>;
	747	+ ranges;
	748	+
	749	+ sdcc@12400000 {
	750	+ status = "disabled";
	751	+ compatible = "arm,pl18x", "arm,primecell";
	752	+ arm,primecell-periphid = <0x00051180>;
	753	+ reg = <0x12400000 0x2000>;
	754	+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	755	+ interrupt-names = "cmd_irq";
	756	+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	757	+ clock-names = "mclk", "apb_pclk";
	758	+ bus-width = <8>;
	759	+ max-frequency = <96000000>;
	760	+ non-removable;
	761	+ cap-sd-highspeed;
	762	+ cap-mmc-highspeed;
	763	+ mmc-ddr-1_8v;
	764	+ vmmc-supply = <&vsdcc_fixed>;
	765	+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
	766	+ dma-names = "tx", "rx";
	767	+ };
	768	+
	769	+ sdcc@12180000 {
	770	+ compatible = "arm,pl18x", "arm,primecell";
	771	+ arm,primecell-periphid = <0x00051180>;
	772	+ status = "disabled";
	773	+ reg = <0x12180000 0x2000>;
	774	+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	775	+ interrupt-names = "cmd_irq";
	776	+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	777	+ clock-names = "mclk", "apb_pclk";
	778	+ bus-width = <8>;
	779	+ cap-sd-highspeed;
	780	+ cap-mmc-highspeed;
	781	+ max-frequency = <192000000>;
	782	+ #mmc-ddr-1_8v;
	783	+ sd-uhs-sdr104;
	784	+ sd-uhs-ddr50;
	785	+ vqmmc-supply = <&vsdcc_fixed>;
	786	+ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
	787	+ dma-names = "tx", "rx";
	788	+ };
	789	+ };
376	790	};
377	791	};