add stmac read mac form eeprom

hc

2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
..
..
@@ -24,46 +24,18 @@
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 			"Headphone Jack", "MICBIAS",
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 			"IN12", "Headphone Jack",
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 			"Speakers", "SPKL",
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-			"Speakers", "SPKR";
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-
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-		assigned-clocks = <&clock CLK_MOUT_EPLL>,
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-				<&clock CLK_MOUT_MAU_EPLL>,
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-				<&clock CLK_MOUT_USER_MAU_EPLL>,
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-				<&clock_audss EXYNOS_MOUT_AUDSS>,
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-				<&clock_audss EXYNOS_MOUT_I2S>,
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-				<&clock_audss EXYNOS_DOUT_SRP>,
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-				<&clock_audss EXYNOS_DOUT_AUD_BUS>,
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-				<&clock_audss EXYNOS_DOUT_I2S>;
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-
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-		assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
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-				<&clock CLK_MOUT_EPLL>,
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-				<&clock CLK_MOUT_MAU_EPLL>,
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-				<&clock CLK_MAU_EPLL>,
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-				<&clock_audss EXYNOS_MOUT_AUDSS>;
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-
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-		assigned-clock-rates = <0>,
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-				<0>,
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-				<0>,
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-				<0>,
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-				<0>,
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-				<196608001>,
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-				<(196608002 / 2)>,
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-				<196608000>;
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+			"Speakers", "SPKR",
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+			"I2S Playback", "Mixer DAI TX",
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+			"HiFi Playback", "Mixer DAI TX",
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+			"Mixer DAI RX", "HiFi Capture";
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 		cpu {
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-			sound-dai = <&i2s0 0>;
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+			sound-dai = <&i2s0 0>, <&i2s0 1>;
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 		};
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 		codec {
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 			sound-dai = <&hdmi>, <&max98090>;
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 		};
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 	};
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-};
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-
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-&clock_audss {
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-	assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
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-			  <&clock CLK_FOUT_EPLL>;
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-	assigned-clock-rates = <(196608000 / 256)>,
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-			       <196608000>;
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 };
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40
 
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 &hsi2c_5 {
..
..
@@ -81,6 +53,31 @@
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53
 
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 &i2s0 {
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 	status = "okay";
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-	assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
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-	assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
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+	assigned-clocks = <&clock CLK_MOUT_EPLL>,
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+			<&clock CLK_MOUT_MAU_EPLL>,
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+			<&clock CLK_MOUT_USER_MAU_EPLL>,
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+			<&clock_audss EXYNOS_MOUT_AUDSS>,
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+			<&clock_audss EXYNOS_MOUT_I2S>,
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+			<&i2s0 CLK_I2S_RCLK_SRC>,
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+			<&clock_audss EXYNOS_DOUT_SRP>,
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+			<&clock_audss EXYNOS_DOUT_AUD_BUS>,
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+			<&clock_audss EXYNOS_DOUT_I2S>;
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+
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+	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
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+			<&clock CLK_MOUT_EPLL>,
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+			<&clock CLK_MOUT_MAU_EPLL>,
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+			<&clock CLK_MAU_EPLL>,
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+			<&clock_audss EXYNOS_MOUT_AUDSS>,
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+			<&clock_audss EXYNOS_SCLK_I2S>;
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+
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+	assigned-clock-rates = <0>,
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+			<0>,
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+			<0>,
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+			<0>,
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+			<0>,
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+			<0>,
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+			<196608001>,
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+			<(196608002 / 2)>,
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+			<196608000>;
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+
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 };