add stmac read mac form eeprom

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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/arch/arm/boot/dts/dra74x.dtsi
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..
@@ -1,9 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
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  *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  * Based on "omap4.dtsi"
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  */
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..
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@@ -31,6 +29,13 @@
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 		};
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 	};
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+	aliases {
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+		rproc0 = &ipu1;
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+		rproc1 = &ipu2;
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+		rproc2 = &dsp1;
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+		rproc3 = &dsp2;
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+	};
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+
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 	pmu {
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 		compatible = "arm,cortex-a15-pmu";
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 		interrupt-parent = <&wakeupgen>;
..
..
@@ -44,48 +49,78 @@
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 			reg = <0x41500000 0x100>;
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 		};
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-		omap_dwc3_4: omap_dwc3_4@48940000 {
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-			compatible = "ti,dwc3";
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-			ti,hwmods = "usb_otg_ss4";
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-			reg = <0x48940000 0x10000>;
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-			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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-			#address-cells = <1>;
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+
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+		target-module@41501000 {
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+			compatible = "ti,sysc-omap2", "ti,sysc";
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+			reg = <0x41501000 0x4>,
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+			      <0x41501010 0x4>,
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+			      <0x41501014 0x4>;
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+			reg-names = "rev", "sysc", "syss";
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>;
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+			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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+					 SYSC_OMAP2_SOFTRESET |
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+					 SYSC_OMAP2_AUTOIDLE)>;
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+			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
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+			clock-names = "fck";
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+			resets = <&prm_dsp2 1>;
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+			reset-names = "rstctrl";
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+			ranges = <0x0 0x41501000 0x1000>;
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 			#size-cells = <1>;
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-			utmi-mode = <2>;
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-			ranges;
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-			status = "disabled";
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-			usb4: usb@48950000 {
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-				compatible = "snps,dwc3";
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-				reg = <0x48950000 0x17000>;
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-				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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-					     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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-					     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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-				interrupt-names = "peripheral",
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-						  "host",
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-						  "otg";
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-				maximum-speed = "high-speed";
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-				dr_mode = "otg";
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+			#address-cells = <1>;
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+
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+			mmu0_dsp2: mmu@0 {
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+				compatible = "ti,dra7-dsp-iommu";
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+				reg = <0x0 0x100>;
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+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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+				#iommu-cells = <0>;
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+				ti,syscon-mmuconfig = <&dsp2_system 0x0>;
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 			};
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 		};
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-		mmu0_dsp2: mmu@41501000 {
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-			compatible = "ti,dra7-dsp-iommu";
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-			reg = <0x41501000 0x100>;
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-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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-			ti,hwmods = "mmu0_dsp2";
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-			#iommu-cells = <0>;
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-			ti,syscon-mmuconfig = <&dsp2_system 0x0>;
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-			status = "disabled";
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+		target-module@41502000 {
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+			compatible = "ti,sysc-omap2", "ti,sysc";
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+			reg = <0x41502000 0x4>,
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+			      <0x41502010 0x4>,
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+			      <0x41502014 0x4>;
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+			reg-names = "rev", "sysc", "syss";
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>;
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+			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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+					 SYSC_OMAP2_SOFTRESET |
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+					 SYSC_OMAP2_AUTOIDLE)>;
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+
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+			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
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+			clock-names = "fck";
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+			resets = <&prm_dsp2 1>;
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+			reset-names = "rstctrl";
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+			ranges = <0x0 0x41502000 0x1000>;
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+			#size-cells = <1>;
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+			#address-cells = <1>;
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+
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+			mmu1_dsp2: mmu@0 {
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+				compatible = "ti,dra7-dsp-iommu";
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+				reg = <0x0 0x100>;
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+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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+				#iommu-cells = <0>;
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+				ti,syscon-mmuconfig = <&dsp2_system 0x1>;
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+			};
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 		};
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-		mmu1_dsp2: mmu@41502000 {
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-			compatible = "ti,dra7-dsp-iommu";
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-			reg = <0x41502000 0x100>;
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-			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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-			ti,hwmods = "mmu1_dsp2";
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-			#iommu-cells = <0>;
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-			ti,syscon-mmuconfig = <&dsp2_system 0x1>;
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+		dsp2: dsp@41000000 {
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+			compatible = "ti,dra7-dsp";
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+			reg = <0x41000000 0x48000>,
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+			      <0x41600000 0x8000>,
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+			      <0x41700000 0x8000>;
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+			reg-names = "l2ram", "l1pram", "l1dram";
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+			ti,bootreg = <&scm_conf 0x560 10>;
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+			iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
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 			status = "disabled";
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+			resets = <&prm_dsp2 0>;
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+			clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
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+			firmware-name = "dra7-dsp2-fw.xe66";
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 		};
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 	};
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 };
..
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@@ -95,27 +130,27 @@
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 };
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 &dss {
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-	reg = <0x58000000 0x80>,
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-	      <0x58004054 0x4>,
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-	      <0x58004300 0x20>,
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-	      <0x58009054 0x4>,
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-	      <0x58009300 0x20>;
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+	reg = <0 0x80>,
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+	      <0x4054 0x4>,
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+	      <0x4300 0x20>,
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+	      <0x9054 0x4>,
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+	      <0x9300 0x20>;
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 	reg-names = "dss", "pll1_clkctrl", "pll1",
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 		    "pll2_clkctrl", "pll2";
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-	clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
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-		 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
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-		 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
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+	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
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+		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
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+		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
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 	clock-names = "fck", "video1_clk", "video2_clk";
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 };
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 &mailbox5 {
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-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
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+	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
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 		ti,mbox-tx = <6 2 2>;
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 		ti,mbox-rx = <4 2 2>;
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 		status = "disabled";
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 	};
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-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
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+	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
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 		ti,mbox-tx = <5 2 2>;
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 		ti,mbox-rx = <1 2 2>;
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 		status = "disabled";
..
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@@ -123,12 +158,12 @@
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 };
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 &mailbox6 {
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-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
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+	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
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 		ti,mbox-tx = <6 2 2>;
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 		ti,mbox-rx = <4 2 2>;
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 		status = "disabled";
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 	};
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-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
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+	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
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 		ti,mbox-tx = <5 2 2>;
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 		ti,mbox-rx = <1 2 2>;
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 		status = "disabled";
..
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@@ -146,3 +181,52 @@
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 &pcie2_rc {
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 	compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
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 };
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+
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+&l4_per3 {
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+	segment@0 {
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+		usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x140000 0x4>,
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+			      <0x140010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>,
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+					<SYSC_IDLE_SMART_WKUP>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>,
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+					<SYSC_IDLE_SMART_WKUP>;
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+			/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
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+			clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x140000 0x20000>;
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+
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+			omap_dwc3_4: omap_dwc3_4@0 {
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+				compatible = "ti,dwc3";
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+				reg = <0 0x10000>;
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+				interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				utmi-mode = <2>;
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+				ranges;
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+				status = "disabled";
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+				usb4: usb@10000 {
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+					compatible = "snps,dwc3";
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+					reg = <0x10000 0x17000>;
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+					interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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+						     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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+						     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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+					interrupt-names = "peripheral",
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+							  "host",
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+							  "otg";
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+					maximum-speed = "high-speed";
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+					dr_mode = "otg";
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+				};
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+			};
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+		};
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+	};
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+};