add stmac read mac form eeprom

hc

2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/arch/arm/boot/dts/bcm-nsp.dtsi
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@@ -34,12 +34,20 @@
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 #include <dt-bindings/interrupt-controller/irq.h>
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 #include <dt-bindings/clock/bcm-nsp.h>
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-#include "skeleton.dtsi"
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-
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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 	compatible = "brcm,nsp";
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 	model = "Broadcom Northstar Plus SoC";
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 	interrupt-parent = <&gic>;
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+
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+	aliases {
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+		serial0 = &uart0;
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+		serial1 = &uart1;
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+		ethernet0 = &amac0;
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+		ethernet1 = &amac1;
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+		ethernet2 = &amac2;
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+	};
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 	cpus {
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 		#address-cells = <1>;
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@@ -69,7 +77,7 @@
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 		interrupt-affinity = <&cpu0>, <&cpu1>;
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 	};
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-	mpcore {
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+	mpcore-bus@19000000 {
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 		compatible = "simple-bus";
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 		ranges = <0x00000000 0x19000000 0x00023000>;
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 		#address-cells = <1>;
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@@ -114,7 +122,7 @@
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 			      <0x20100 0x100>;
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 		};
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-		L2: l2-cache {
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+		L2: cache-controller@22000 {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x22000 0x1000>;
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 			cache-unified;
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@@ -158,7 +166,7 @@
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 		};
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 	};
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-	axi {
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+	axi@18000000 {
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 		compatible = "simple-bus";
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 		ranges = <0x00000000 0x18000000 0x0011c40c>;
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 		#address-cells = <1>;
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@@ -192,7 +200,7 @@
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 			status = "disabled";
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 		};
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-		dma@20000 {
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+		dma: dma@20000 {
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 			compatible = "arm,pl330", "arm,primecell";
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 			reg = <0x20000 0x1000>;
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 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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@@ -207,9 +215,11 @@
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 			clocks = <&iprocslow>;
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 			clock-names = "apb_pclk";
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 			#dma-cells = <1>;
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+			dma-coherent;
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+			status = "disabled";
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 		};
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-		sdio: sdhci@21000 {
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+		sdio: mmc@21000 {
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 			compatible = "brcm,sdhci-iproc-cygnus";
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 			reg = <0x21000 0x100>;
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 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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@@ -358,7 +368,7 @@
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 		};
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369
 
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 		ccbtimer0: timer@34000 {
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-			compatible = "arm,sp804";
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+			compatible = "arm,sp804", "arm,primecell";
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 			reg = <0x34000 0x1000>;
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 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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 				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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@@ -367,7 +377,7 @@
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 		};
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 		ccbtimer1: timer@35000 {
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-			compatible = "arm,sp804";
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+			compatible = "arm,sp804", "arm,primecell";
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 			reg = <0x35000 0x1000>;
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 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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 				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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@@ -377,10 +387,36 @@
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 		srab: srab@36000 {
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 			compatible = "brcm,nsp-srab";
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-			reg = <0x36000 0x1000>;
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-			#address-cells = <1>;
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-			#size-cells = <0>;
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-
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+			reg = <0x36000 0x1000>,
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+			      <0x3f308 0x8>,
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+			      <0x3f410 0xc>;
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+			reg-names = "srab", "mux_config", "sgmii";
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+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "link_state_p0",
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+					  "link_state_p1",
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+					  "link_state_p2",
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+					  "link_state_p3",
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+					  "link_state_p4",
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+					  "link_state_p5",
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+					  "link_state_p7",
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+					  "link_state_p8",
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+					  "phy",
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+					  "ts",
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+					  "imp_sleep_timer_p5",
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+					  "imp_sleep_timer_p7",
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+					  "imp_sleep_timer_p8";
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 			status = "disabled";
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 			/* ports are defined in board DTS */
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@@ -402,7 +438,7 @@
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 			reg = <0x39000 0x1000>;
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 			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&iprocslow>, <&iprocslow>;
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-			clock-names = "wdogclk", "apb_pclk";
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+			clock-names = "wdog_clk", "apb_pclk";
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 		};
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 		lcpll0: lcpll0@3f100 {