.. | .. |
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26 | 26 | struct regmap *regmap[RSND_BASE_MAX]; |
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27 | 27 | |
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28 | 28 | /* RSND_REG_MAX base */ |
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29 | | - struct regmap_field *regs[RSND_REG_MAX]; |
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30 | | - const char *reg_name[RSND_REG_MAX]; |
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| 29 | + struct regmap_field *regs[REG_MAX]; |
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| 30 | + const char *reg_name[REG_MAX]; |
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31 | 31 | }; |
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32 | 32 | |
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33 | 33 | #define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen) |
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.. | .. |
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49 | 49 | } |
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50 | 50 | /* single address mapping */ |
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51 | 51 | #define RSND_GEN_S_REG(id, offset) \ |
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52 | | - RSND_REG_SET(RSND_REG_##id, offset, 0, #id) |
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| 52 | + RSND_REG_SET(id, offset, 0, #id) |
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53 | 53 | |
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54 | 54 | /* multi address mapping */ |
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55 | 55 | #define RSND_GEN_M_REG(id, offset, _id_offset) \ |
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56 | | - RSND_REG_SET(RSND_REG_##id, offset, _id_offset, #id) |
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| 56 | + RSND_REG_SET(id, offset, _id_offset, #id) |
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57 | 57 | |
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58 | 58 | /* |
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59 | 59 | * basic function |
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.. | .. |
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71 | 71 | return 1; |
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72 | 72 | } |
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73 | 73 | |
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74 | | -u32 rsnd_read(struct rsnd_priv *priv, |
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75 | | - struct rsnd_mod *mod, enum rsnd_reg reg) |
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| 74 | +static int rsnd_mod_id_cmd(struct rsnd_mod *mod) |
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76 | 75 | { |
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| 76 | + if (mod->ops->id_cmd) |
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| 77 | + return mod->ops->id_cmd(mod); |
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| 78 | + |
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| 79 | + return rsnd_mod_id(mod); |
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| 80 | +} |
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| 81 | + |
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| 82 | +u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg) |
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| 83 | +{ |
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| 84 | + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); |
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77 | 85 | struct device *dev = rsnd_priv_to_dev(priv); |
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78 | 86 | struct rsnd_gen *gen = rsnd_priv_to_gen(priv); |
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79 | 87 | u32 val; |
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.. | .. |
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81 | 89 | if (!rsnd_is_accessible_reg(priv, gen, reg)) |
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82 | 90 | return 0; |
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83 | 91 | |
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84 | | - regmap_fields_read(gen->regs[reg], rsnd_mod_id(mod), &val); |
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| 92 | + regmap_fields_read(gen->regs[reg], rsnd_mod_id_cmd(mod), &val); |
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85 | 93 | |
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86 | | - dev_dbg(dev, "r %s[%d] - %-18s (%4d) : %08x\n", |
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87 | | - rsnd_mod_name(mod), rsnd_mod_id(mod), |
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| 94 | + dev_dbg(dev, "r %s - %-18s (%4d) : %08x\n", |
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| 95 | + rsnd_mod_name(mod), |
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88 | 96 | rsnd_reg_name(gen, reg), reg, val); |
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89 | 97 | |
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90 | 98 | return val; |
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91 | 99 | } |
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92 | 100 | |
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93 | | -void rsnd_write(struct rsnd_priv *priv, |
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94 | | - struct rsnd_mod *mod, |
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95 | | - enum rsnd_reg reg, u32 data) |
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| 101 | +void rsnd_mod_write(struct rsnd_mod *mod, |
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| 102 | + enum rsnd_reg reg, u32 data) |
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96 | 103 | { |
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| 104 | + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); |
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97 | 105 | struct device *dev = rsnd_priv_to_dev(priv); |
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98 | 106 | struct rsnd_gen *gen = rsnd_priv_to_gen(priv); |
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99 | 107 | |
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100 | 108 | if (!rsnd_is_accessible_reg(priv, gen, reg)) |
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101 | 109 | return; |
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102 | 110 | |
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103 | | - regmap_fields_force_write(gen->regs[reg], rsnd_mod_id(mod), data); |
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| 111 | + regmap_fields_force_write(gen->regs[reg], rsnd_mod_id_cmd(mod), data); |
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104 | 112 | |
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105 | | - dev_dbg(dev, "w %s[%d] - %-18s (%4d) : %08x\n", |
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106 | | - rsnd_mod_name(mod), rsnd_mod_id(mod), |
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| 113 | + dev_dbg(dev, "w %s - %-18s (%4d) : %08x\n", |
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| 114 | + rsnd_mod_name(mod), |
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107 | 115 | rsnd_reg_name(gen, reg), reg, data); |
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108 | 116 | } |
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109 | 117 | |
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110 | | -void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, |
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111 | | - enum rsnd_reg reg, u32 mask, u32 data) |
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| 118 | +void rsnd_mod_bset(struct rsnd_mod *mod, |
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| 119 | + enum rsnd_reg reg, u32 mask, u32 data) |
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112 | 120 | { |
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| 121 | + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); |
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113 | 122 | struct device *dev = rsnd_priv_to_dev(priv); |
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114 | 123 | struct rsnd_gen *gen = rsnd_priv_to_gen(priv); |
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115 | 124 | |
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.. | .. |
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117 | 126 | return; |
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118 | 127 | |
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119 | 128 | regmap_fields_force_update_bits(gen->regs[reg], |
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120 | | - rsnd_mod_id(mod), mask, data); |
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| 129 | + rsnd_mod_id_cmd(mod), mask, data); |
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121 | 130 | |
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122 | | - dev_dbg(dev, "b %s[%d] - %-18s (%4d) : %08x/%08x\n", |
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123 | | - rsnd_mod_name(mod), rsnd_mod_id(mod), |
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| 131 | + dev_dbg(dev, "b %s - %-18s (%4d) : %08x/%08x\n", |
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| 132 | + rsnd_mod_name(mod), |
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124 | 133 | rsnd_reg_name(gen, reg), reg, data, mask); |
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125 | 134 | |
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126 | 135 | } |
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.. | .. |
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215 | 224 | RSND_GEN_S_REG(SSI_SYS_STATUS5, 0x884), |
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216 | 225 | RSND_GEN_S_REG(SSI_SYS_STATUS6, 0x888), |
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217 | 226 | RSND_GEN_S_REG(SSI_SYS_STATUS7, 0x88c), |
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| 227 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850), |
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| 228 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE1, 0x854), |
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| 229 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858), |
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| 230 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE3, 0x85c), |
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| 231 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890), |
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| 232 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE5, 0x894), |
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| 233 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE6, 0x898), |
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| 234 | + RSND_GEN_S_REG(SSI_SYS_INT_ENABLE7, 0x89c), |
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218 | 235 | RSND_GEN_S_REG(HDMI0_SEL, 0x9e0), |
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219 | 236 | RSND_GEN_S_REG(HDMI1_SEL, 0x9e4), |
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220 | 237 | |
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221 | 238 | /* FIXME: it needs SSI_MODE2/3 in the future */ |
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222 | | - RSND_GEN_M_REG(SSI_BUSIF_MODE, 0x0, 0x80), |
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223 | | - RSND_GEN_M_REG(SSI_BUSIF_ADINR, 0x4, 0x80), |
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224 | | - RSND_GEN_M_REG(SSI_BUSIF_DALIGN,0x8, 0x80), |
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225 | | - RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80), |
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226 | | - RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), |
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227 | | - RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80), |
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| 239 | + RSND_GEN_M_REG(SSI_BUSIF0_MODE, 0x0, 0x80), |
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| 240 | + RSND_GEN_M_REG(SSI_BUSIF0_ADINR, 0x4, 0x80), |
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| 241 | + RSND_GEN_M_REG(SSI_BUSIF0_DALIGN, 0x8, 0x80), |
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| 242 | + RSND_GEN_M_REG(SSI_BUSIF1_MODE, 0x20, 0x80), |
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| 243 | + RSND_GEN_M_REG(SSI_BUSIF1_ADINR, 0x24, 0x80), |
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| 244 | + RSND_GEN_M_REG(SSI_BUSIF1_DALIGN, 0x28, 0x80), |
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| 245 | + RSND_GEN_M_REG(SSI_BUSIF2_MODE, 0x40, 0x80), |
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| 246 | + RSND_GEN_M_REG(SSI_BUSIF2_ADINR, 0x44, 0x80), |
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| 247 | + RSND_GEN_M_REG(SSI_BUSIF2_DALIGN, 0x48, 0x80), |
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| 248 | + RSND_GEN_M_REG(SSI_BUSIF3_MODE, 0x60, 0x80), |
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| 249 | + RSND_GEN_M_REG(SSI_BUSIF3_ADINR, 0x64, 0x80), |
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| 250 | + RSND_GEN_M_REG(SSI_BUSIF3_DALIGN, 0x68, 0x80), |
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| 251 | + RSND_GEN_M_REG(SSI_BUSIF4_MODE, 0x500, 0x80), |
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| 252 | + RSND_GEN_M_REG(SSI_BUSIF4_ADINR, 0x504, 0x80), |
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| 253 | + RSND_GEN_M_REG(SSI_BUSIF4_DALIGN, 0x508, 0x80), |
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| 254 | + RSND_GEN_M_REG(SSI_BUSIF5_MODE, 0x520, 0x80), |
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| 255 | + RSND_GEN_M_REG(SSI_BUSIF5_ADINR, 0x524, 0x80), |
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| 256 | + RSND_GEN_M_REG(SSI_BUSIF5_DALIGN, 0x528, 0x80), |
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| 257 | + RSND_GEN_M_REG(SSI_BUSIF6_MODE, 0x540, 0x80), |
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| 258 | + RSND_GEN_M_REG(SSI_BUSIF6_ADINR, 0x544, 0x80), |
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| 259 | + RSND_GEN_M_REG(SSI_BUSIF6_DALIGN, 0x548, 0x80), |
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| 260 | + RSND_GEN_M_REG(SSI_BUSIF7_MODE, 0x560, 0x80), |
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| 261 | + RSND_GEN_M_REG(SSI_BUSIF7_ADINR, 0x564, 0x80), |
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| 262 | + RSND_GEN_M_REG(SSI_BUSIF7_DALIGN, 0x568, 0x80), |
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| 263 | + RSND_GEN_M_REG(SSI_MODE, 0xc, 0x80), |
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| 264 | + RSND_GEN_M_REG(SSI_CTRL, 0x10, 0x80), |
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| 265 | + RSND_GEN_M_REG(SSI_INT_ENABLE, 0x18, 0x80), |
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| 266 | + RSND_GEN_S_REG(SSI9_BUSIF0_MODE, 0x48c), |
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| 267 | + RSND_GEN_S_REG(SSI9_BUSIF0_ADINR, 0x484), |
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| 268 | + RSND_GEN_S_REG(SSI9_BUSIF0_DALIGN, 0x488), |
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| 269 | + RSND_GEN_S_REG(SSI9_BUSIF1_MODE, 0x4a0), |
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| 270 | + RSND_GEN_S_REG(SSI9_BUSIF1_ADINR, 0x4a4), |
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| 271 | + RSND_GEN_S_REG(SSI9_BUSIF1_DALIGN, 0x4a8), |
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| 272 | + RSND_GEN_S_REG(SSI9_BUSIF2_MODE, 0x4c0), |
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| 273 | + RSND_GEN_S_REG(SSI9_BUSIF2_ADINR, 0x4c4), |
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| 274 | + RSND_GEN_S_REG(SSI9_BUSIF2_DALIGN, 0x4c8), |
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| 275 | + RSND_GEN_S_REG(SSI9_BUSIF3_MODE, 0x4e0), |
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| 276 | + RSND_GEN_S_REG(SSI9_BUSIF3_ADINR, 0x4e4), |
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| 277 | + RSND_GEN_S_REG(SSI9_BUSIF3_DALIGN, 0x4e8), |
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| 278 | + RSND_GEN_S_REG(SSI9_BUSIF4_MODE, 0xd80), |
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| 279 | + RSND_GEN_S_REG(SSI9_BUSIF4_ADINR, 0xd84), |
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| 280 | + RSND_GEN_S_REG(SSI9_BUSIF4_DALIGN, 0xd88), |
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| 281 | + RSND_GEN_S_REG(SSI9_BUSIF5_MODE, 0xda0), |
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| 282 | + RSND_GEN_S_REG(SSI9_BUSIF5_ADINR, 0xda4), |
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| 283 | + RSND_GEN_S_REG(SSI9_BUSIF5_DALIGN, 0xda8), |
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| 284 | + RSND_GEN_S_REG(SSI9_BUSIF6_MODE, 0xdc0), |
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| 285 | + RSND_GEN_S_REG(SSI9_BUSIF6_ADINR, 0xdc4), |
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| 286 | + RSND_GEN_S_REG(SSI9_BUSIF6_DALIGN, 0xdc8), |
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| 287 | + RSND_GEN_S_REG(SSI9_BUSIF7_MODE, 0xde0), |
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| 288 | + RSND_GEN_S_REG(SSI9_BUSIF7_ADINR, 0xde4), |
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| 289 | + RSND_GEN_S_REG(SSI9_BUSIF7_DALIGN, 0xde8), |
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228 | 290 | }; |
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229 | 291 | |
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230 | 292 | static const struct rsnd_regmap_field_conf conf_scu[] = { |
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