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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/sound/soc/fsl/fsl_asrc.h
....@@ -10,8 +10,7 @@
1010 #ifndef _FSL_ASRC_H
1111 #define _FSL_ASRC_H
1212 
13
-#define IN	0
14
-#define OUT	1
13
+#include  "fsl_asrc_common.h"
1514 
1615 #define ASRC_DMA_BUFFER_NUM		2
1716 #define ASRC_INPUTFIFO_THRESHOLD	32
....@@ -283,14 +282,6 @@
283282 #define ASRMCR1i_OW16_MASK		(1 << ASRMCR1i_OW16_SHIFT)
284283 #define ASRMCR1i_OW16(v)		((v) << ASRMCR1i_OW16_SHIFT)
285284 
286
-
287
-enum asrc_pair_index {
288
-	ASRC_INVALID_PAIR = -1,
289
-	ASRC_PAIR_A = 0,
290
-	ASRC_PAIR_B = 1,
291
-	ASRC_PAIR_C = 2,
292
-};
293
-
294285 #define ASRC_PAIR_MAX_NUM	(ASRC_PAIR_C + 1)
295286 
296287 enum asrc_inclk {
....@@ -308,6 +299,29 @@
308299 	INCLK_SSI3_TX = 0x0b,
309300 	INCLK_SPDIF_TX = 0x0c,
310301 	INCLK_ASRCK1_CLK = 0x0f,
302
+
303
+	/* clocks for imx8 */
304
+	INCLK_AUD_PLL_DIV_CLK0 = 0x10,
305
+	INCLK_AUD_PLL_DIV_CLK1 = 0x11,
306
+	INCLK_AUD_CLK0         = 0x12,
307
+	INCLK_AUD_CLK1         = 0x13,
308
+	INCLK_ESAI0_RX_CLK     = 0x14,
309
+	INCLK_ESAI0_TX_CLK     = 0x15,
310
+	INCLK_SPDIF0_RX        = 0x16,
311
+	INCLK_SPDIF1_RX        = 0x17,
312
+	INCLK_SAI0_RX_BCLK     = 0x18,
313
+	INCLK_SAI0_TX_BCLK     = 0x19,
314
+	INCLK_SAI1_RX_BCLK     = 0x1a,
315
+	INCLK_SAI1_TX_BCLK     = 0x1b,
316
+	INCLK_SAI2_RX_BCLK     = 0x1c,
317
+	INCLK_SAI3_RX_BCLK     = 0x1d,
318
+	INCLK_ASRC0_MUX_CLK    = 0x1e,
319
+
320
+	INCLK_ESAI1_RX_CLK     = 0x20,
321
+	INCLK_ESAI1_TX_CLK     = 0x21,
322
+	INCLK_SAI6_TX_BCLK     = 0x22,
323
+	INCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
324
+	INCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
311325 };
312326 
313327 enum asrc_outclk {
....@@ -325,9 +339,33 @@
325339 	OUTCLK_SSI3_RX = 0x0b,
326340 	OUTCLK_SPDIF_RX = 0x0c,
327341 	OUTCLK_ASRCK1_CLK = 0x0f,
342
+
343
+	/* clocks for imx8 */
344
+	OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
345
+	OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
346
+	OUTCLK_AUD_CLK0         = 0x12,
347
+	OUTCLK_AUD_CLK1         = 0x13,
348
+	OUTCLK_ESAI0_RX_CLK     = 0x14,
349
+	OUTCLK_ESAI0_TX_CLK     = 0x15,
350
+	OUTCLK_SPDIF0_RX        = 0x16,
351
+	OUTCLK_SPDIF1_RX        = 0x17,
352
+	OUTCLK_SAI0_RX_BCLK     = 0x18,
353
+	OUTCLK_SAI0_TX_BCLK     = 0x19,
354
+	OUTCLK_SAI1_RX_BCLK     = 0x1a,
355
+	OUTCLK_SAI1_TX_BCLK     = 0x1b,
356
+	OUTCLK_SAI2_RX_BCLK     = 0x1c,
357
+	OUTCLK_SAI3_RX_BCLK     = 0x1d,
358
+	OUTCLK_ASRCO_MUX_CLK    = 0x1e,
359
+
360
+	OUTCLK_ESAI1_RX_CLK     = 0x20,
361
+	OUTCLK_ESAI1_TX_CLK     = 0x21,
362
+	OUTCLK_SAI6_TX_BCLK     = 0x22,
363
+	OUTCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
364
+	OUTCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
328365 };
329366 
330367 #define ASRC_CLK_MAX_NUM	16
368
+#define ASRC_CLK_MAP_LEN	0x30
331369 
332370 enum asrc_word_width {
333371 	ASRC_WIDTH_24_BIT = 0,
....@@ -342,8 +380,8 @@
342380 	unsigned int dma_buffer_size;
343381 	unsigned int input_sample_rate;
344382 	unsigned int output_sample_rate;
345
-	enum asrc_word_width input_word_width;
346
-	enum asrc_word_width output_word_width;
383
+	snd_pcm_format_t input_format;
384
+	snd_pcm_format_t output_format;
347385 	enum asrc_inclk inclk;
348386 	enum asrc_outclk outclk;
349387 };
....@@ -388,78 +426,39 @@
388426 };
389427 
390428 /**
391
- * fsl_asrc_pair: ASRC Pair private data
429
+ * fsl_asrc_soc_data: soc specific data
392430  *
393
- * @asrc_priv: pointer to its parent module
394
- * @config: configuration profile
395
- * @error: error record
396
- * @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
397
- * @channels: occupied channel number
398
- * @desc: input and output dma descriptors
399
- * @dma_chan: inputer and output DMA channels
400
- * @dma_data: private dma data
401
- * @pos: hardware pointer position
402
- * @private: pair private area
431
+ * @use_edma: using edma as dma device or not
432
+ * @channel_bits: width of ASRCNCR register for each pair
403433  */
404
-struct fsl_asrc_pair {
405
-	struct fsl_asrc *asrc_priv;
406
-	struct asrc_config *config;
407
-	unsigned int error;
408
-
409
-	enum asrc_pair_index index;
410
-	unsigned int channels;
411
-
412
-	struct dma_async_tx_descriptor *desc[2];
413
-	struct dma_chan *dma_chan[2];
414
-	struct imx_dma_data dma_data;
415
-	unsigned int pos;
416
-
417
-	void *private;
434
+struct fsl_asrc_soc_data {
435
+	bool use_edma;
436
+	unsigned int channel_bits;
418437 };
419438 
420439 /**
421
- * fsl_asrc_pair: ASRC private data
440
+ * fsl_asrc_pair_priv: ASRC Pair private data
422441  *
423
- * @dma_params_rx: DMA parameters for receive channel
424
- * @dma_params_tx: DMA parameters for transmit channel
425
- * @pdev: platform device pointer
426
- * @regmap: regmap handler
427
- * @paddr: physical address to the base address of registers
428
- * @mem_clk: clock source to access register
429
- * @ipg_clk: clock source to drive peripheral
430
- * @spba_clk: SPBA clock (optional, depending on SoC design)
442
+ * @config: configuration profile
443
+ */
444
+struct fsl_asrc_pair_priv {
445
+	struct asrc_config *config;
446
+};
447
+
448
+/**
449
+ * fsl_asrc_priv: ASRC private data
450
+ *
431451  * @asrck_clk: clock sources to driver ASRC internal logic
432
- * @lock: spin lock for resource protection
433
- * @pair: pair pointers
434
- * @channel_bits: width of ASRCNCR register for each pair
435
- * @channel_avail: non-occupied channel numbers
436
- * @asrc_rate: default sample rate for ASoC Back-Ends
437
- * @asrc_width: default sample width for ASoC Back-Ends
452
+ * @soc: soc specific data
453
+ * @clk_map: clock map for input/output clock
438454  * @regcache_cfg: store register value of REG_ASRCFG
439455  */
440
-struct fsl_asrc {
441
-	struct snd_dmaengine_dai_dma_data dma_params_rx;
442
-	struct snd_dmaengine_dai_dma_data dma_params_tx;
443
-	struct platform_device *pdev;
444
-	struct regmap *regmap;
445
-	unsigned long paddr;
446
-	struct clk *mem_clk;
447
-	struct clk *ipg_clk;
448
-	struct clk *spba_clk;
456
+struct fsl_asrc_priv {
449457 	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
450
-	spinlock_t lock;
451
-
452
-	struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
453
-	unsigned int channel_bits;
454
-	unsigned int channel_avail;
455
-
456
-	int asrc_rate;
457
-	int asrc_width;
458
+	const struct fsl_asrc_soc_data *soc;
459
+	unsigned char *clk_map[2];
458460 
459461 	u32 regcache_cfg;
460462 };
461463 
462
-#define DRV_NAME "fsl-asrc-dai"
463
-extern struct snd_soc_component_driver fsl_asrc_component;
464
-struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir);
465464 #endif /* _FSL_ASRC_H */