修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/include/uapi/drm/v3d_drm.h
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@@ -36,6 +36,8 @@
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 #define DRM_V3D_MMAP_BO                           0x03
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 #define DRM_V3D_GET_PARAM                         0x04
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 #define DRM_V3D_GET_BO_OFFSET                     0x05
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+#define DRM_V3D_SUBMIT_TFU                        0x06
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+#define DRM_V3D_SUBMIT_CSD                        0x07
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 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
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 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
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@@ -43,6 +45,10 @@
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 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
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 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
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 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
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+#define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
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+#define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
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+
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+#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE             0x01
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 /**
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  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
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@@ -50,6 +56,14 @@
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  *
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  * This asks the kernel to have the GPU execute an optional binner
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  * command list, and a render command list.
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+ *
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+ * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
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+ * each CL executes.  The VCD cache should be flushed (if necessary)
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+ * by the submitted CLs.  The TLB writes are guaranteed to have been
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+ * flushed by the time the render done IRQ happens, which is the
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+ * trigger for out_sync.  Any dirtying of cachelines by the job (only
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+ * possible using TMU writes) must be flushed by the caller using the
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+ * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
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  */
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 struct drm_v3d_submit_cl {
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 	/* Pointer to the binner command list.
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@@ -58,10 +72,15 @@
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 	 * coordinate shader to determine where primitives land on the screen,
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 	 * then writes out the state updates and draw calls necessary per tile
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 	 * to the tile allocation BO.
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+	 *
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+	 * This BCL will block on any previous BCL submitted on the
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+	 * same FD, but not on any RCL or BCLs submitted by other
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+	 * clients -- that is left up to the submitter to control
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+	 * using in_sync_bcl if necessary.
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 	 */
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 	__u32 bcl_start;
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-	 /** End address of the BCL (first byte after the BCL) */
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+	/** End address of the BCL (first byte after the BCL) */
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 	__u32 bcl_end;
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 	/* Offset of the render command list.
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@@ -69,10 +88,15 @@
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 	 * This is the second set of commands executed, which will either
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 	 * execute the tiles that have been set up by the BCL, or a fixed set
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 	 * of tiles (in the case of RCL-only blits).
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+	 *
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+	 * This RCL will block on this submit's BCL, and any previous
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+	 * RCL submitted on the same FD, but not on any RCL or BCLs
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+	 * submitted by other clients -- that is left up to the
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+	 * submitter to control using in_sync_rcl if necessary.
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 	 */
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 	__u32 rcl_start;
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-	 /** End address of the RCL (first byte after the RCL) */
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+	/** End address of the RCL (first byte after the RCL) */
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 	__u32 rcl_end;
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 	/** An optional sync object to wait on before starting the BCL. */
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@@ -102,8 +126,7 @@
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 	/* Number of BO handles passed in (size is that times 4). */
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 	__u32 bo_handle_count;
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-	/* Pad, must be zero-filled. */
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-	__u32 pad;
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+	__u32 flags;
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 };
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 /**
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@@ -169,6 +192,9 @@
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 	DRM_V3D_PARAM_V3D_CORE0_IDENT0,
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 	DRM_V3D_PARAM_V3D_CORE0_IDENT1,
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 	DRM_V3D_PARAM_V3D_CORE0_IDENT2,
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+	DRM_V3D_PARAM_SUPPORTS_TFU,
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+	DRM_V3D_PARAM_SUPPORTS_CSD,
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+	DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
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 };
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 struct drm_v3d_get_param {
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@@ -187,6 +213,53 @@
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 	__u32 offset;
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 };
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+struct drm_v3d_submit_tfu {
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+	__u32 icfg;
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+	__u32 iia;
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+	__u32 iis;
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+	__u32 ica;
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+	__u32 iua;
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+	__u32 ioa;
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+	__u32 ios;
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+	__u32 coef[4];
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+	/* First handle is the output BO, following are other inputs.
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+	 * 0 for unused.
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+	 */
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+	__u32 bo_handles[4];
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+	/* sync object to block on before running the TFU job.  Each TFU
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+	 * job will execute in the order submitted to its FD.  Synchronization
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+	 * against rendering jobs requires using sync objects.
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+	 */
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+	__u32 in_sync;
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+	/* Sync object to signal when the TFU job is done. */
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+	__u32 out_sync;
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+};
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+
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+/* Submits a compute shader for dispatch.  This job will block on any
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+ * previous compute shaders submitted on this fd, and any other
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+ * synchronization must be performed with in_sync/out_sync.
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+ */
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+struct drm_v3d_submit_csd {
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+	__u32 cfg[7];
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+	__u32 coef[4];
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+
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+	/* Pointer to a u32 array of the BOs that are referenced by the job.
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+	 */
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+	__u64 bo_handles;
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+
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+	/* Number of BO handles passed in (size is that times 4). */
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+	__u32 bo_handle_count;
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+
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+	/* sync object to block on before running the CSD job.  Each
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+	 * CSD job will execute in the order submitted to its FD.
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+	 * Synchronization against rendering/TFU jobs or CSD from
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+	 * other fds requires using sync objects.
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+	 */
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+	__u32 in_sync;
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+	/* Sync object to signal when the CSD job is done. */
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+	__u32 out_sync;
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+};
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+
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 #if defined(__cplusplus)
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 }
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 #endif