修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/usb/phy/phy-mxs-usb.c
..
..
@@ -17,9 +17,11 @@
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 #include <linux/of_device.h>
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 #include <linux/regmap.h>
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 #include <linux/mfd/syscon.h>
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+#include <linux/iopoll.h>
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21
 
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 #define DRIVER_NAME "mxs_phy"
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23
 
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+/* Register Macro */
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 #define HW_USBPHY_PWD				0x00
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 #define HW_USBPHY_TX				0x10
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 #define HW_USBPHY_CTRL				0x30
..
..
@@ -36,6 +38,11 @@
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 #define GM_USBPHY_TX_TXCAL45DP(x)            (((x) & 0xf) << 16)
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 #define GM_USBPHY_TX_TXCAL45DN(x)            (((x) & 0xf) << 8)
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 #define GM_USBPHY_TX_D_CAL(x)                (((x) & 0xf) << 0)
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+
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+/* imx7ulp */
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+#define HW_USBPHY_PLL_SIC			0xa0
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+#define HW_USBPHY_PLL_SIC_SET			0xa4
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+#define HW_USBPHY_PLL_SIC_CLR			0xa8
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46
 
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 #define BM_USBPHY_CTRL_SFTRST			BIT(31)
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 #define BM_USBPHY_CTRL_CLKGATE			BIT(30)
..
..
@@ -55,6 +62,12 @@
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 #define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))
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63
 
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 #define BM_USBPHY_DEBUG_CLKGATE			BIT(30)
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+/* imx7ulp */
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+#define BM_USBPHY_PLL_LOCK			BIT(31)
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+#define BM_USBPHY_PLL_REG_ENABLE		BIT(21)
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+#define BM_USBPHY_PLL_BYPASS			BIT(16)
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+#define BM_USBPHY_PLL_POWER			BIT(12)
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+#define BM_USBPHY_PLL_EN_USB_CLKS		BIT(6)
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71
 
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 /* Anatop Registers */
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 #define ANADIG_ANA_MISC0			0x150
..
..
@@ -63,6 +76,7 @@
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76
 
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 #define ANADIG_USB1_CHRG_DETECT_SET		0x1b4
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 #define ANADIG_USB1_CHRG_DETECT_CLR		0x1b8
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+#define ANADIG_USB2_CHRG_DETECT_SET		0x214
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 #define ANADIG_USB1_CHRG_DETECT_EN_B		BIT(20)
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 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B	BIT(19)
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 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT	BIT(18)
..
..
@@ -167,6 +181,9 @@
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 	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
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 };
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183
 
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+static const struct mxs_phy_data imx7ulp_phy_data = {
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+};
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+
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 static const struct of_device_id mxs_phy_dt_ids[] = {
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 	{ .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
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 	{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
..
..
@@ -174,6 +191,7 @@
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 	{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
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 	{ .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
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 	{ .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, },
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+	{ .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, },
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 	{ /* sentinel */ }
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 };
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 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
..
..
@@ -196,6 +214,11 @@
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 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
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 {
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 	return mxs_phy->data == &imx6sl_phy_data;
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+}
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+
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+static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy)
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+{
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+	return mxs_phy->data == &imx7ulp_phy_data;
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 }
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 /*
..
..
@@ -221,14 +244,49 @@
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 	}
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 }
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246
 
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+static int mxs_phy_pll_enable(void __iomem *base, bool enable)
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+{
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+	int ret = 0;
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+
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+	if (enable) {
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+		u32 value;
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+
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+		writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET);
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+		writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR);
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+		writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET);
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+		ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC,
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+			value, (value & BM_USBPHY_PLL_LOCK) != 0,
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+			100, 10000);
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+		if (ret)
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+			return ret;
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+
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+		writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
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+				HW_USBPHY_PLL_SIC_SET);
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+	} else {
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+		writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
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+				HW_USBPHY_PLL_SIC_CLR);
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+		writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR);
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+		writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET);
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+		writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR);
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+	}
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+
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+	return ret;
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+}
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+
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 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
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 {
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 	int ret;
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 	void __iomem *base = mxs_phy->phy.io_priv;
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+	if (is_imx7ulp_phy(mxs_phy)) {
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+		ret = mxs_phy_pll_enable(base, true);
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+		if (ret)
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+			return ret;
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+	}
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+
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 	ret = stmp_reset_block(base + HW_USBPHY_CTRL);
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 	if (ret)
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-		return ret;
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+		goto disable_pll;
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 	/* Power up the PHY */
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 	writel(0, base + HW_USBPHY_PWD);
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@@ -250,9 +308,27 @@
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 	if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
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 		writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
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+	if (mxs_phy->regmap_anatop) {
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+		unsigned int reg = mxs_phy->port_id ?
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+			ANADIG_USB1_CHRG_DETECT_SET :
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+			ANADIG_USB2_CHRG_DETECT_SET;
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+		/*
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+		 * The external charger detector needs to be disabled,
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+		 * or the signal at DP will be poor
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+		 */
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+		regmap_write(mxs_phy->regmap_anatop, reg,
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+			     ANADIG_USB1_CHRG_DETECT_EN_B |
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+			     ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
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+	}
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+
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 	mxs_phy_tx_init(mxs_phy);
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 	return 0;
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+
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+disable_pll:
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+	if (is_imx7ulp_phy(mxs_phy))
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+		mxs_phy_pll_enable(base, false);
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+	return ret;
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 }
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 /* Return true if the vbus is there */
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@@ -312,14 +388,8 @@
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388
 
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 static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
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 {
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-	void __iomem *base = mxs_phy->phy.io_priv;
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-	u32 phyctrl = readl(base + HW_USBPHY_CTRL);
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-
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-	if (IS_ENABLED(CONFIG_USB_OTG) &&
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-			!(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE))
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-		return true;
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-
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-	return false;
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+	return IS_ENABLED(CONFIG_USB_OTG) &&
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+		mxs_phy->phy.last_event == USB_EVENT_ID;
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 }
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 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
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@@ -373,6 +443,9 @@
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443
 
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 	writel(BM_USBPHY_CTRL_CLKGATE,
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 	       phy->io_priv + HW_USBPHY_CTRL_SET);
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+
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+	if (is_imx7ulp_phy(mxs_phy))
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+		mxs_phy_pll_enable(phy->io_priv, false);
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449
 
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 	clk_disable_unprepare(mxs_phy->clk);
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 }
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@@ -563,7 +636,7 @@
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 	regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val);
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 	if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) {
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 		chgr_type = SDP_TYPE;
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-		dev_dbg(x->phy.dev, "It is a stardard downstream port\n");
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+		dev_dbg(x->phy.dev, "It is a standard downstream port\n");
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 	}
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641
 
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 	/* Disable charger detector */
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@@ -631,7 +704,6 @@
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 static int mxs_phy_probe(struct platform_device *pdev)
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 {
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-	struct resource *res;
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 	void __iomem *base;
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 	struct clk *clk;
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 	struct mxs_phy *mxs_phy;
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@@ -644,8 +716,7 @@
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 	if (!of_id)
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 		return -ENODEV;
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	base = devm_ioremap_resource(&pdev->dev, res);
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+	base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(base))
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 		return PTR_ERR(base);
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