.. | .. |
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6 | 6 | */ |
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7 | 7 | |
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8 | 8 | #include <linux/firmware.h> |
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| 9 | +#include <linux/iopoll.h> |
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9 | 10 | #include <linux/module.h> |
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10 | 11 | #include <linux/platform_device.h> |
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11 | 12 | #include <linux/of.h> |
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.. | .. |
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74 | 75 | |
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75 | 76 | /* For soc_device_attribute */ |
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76 | 77 | #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */ |
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77 | | -#define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */ |
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78 | 78 | |
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79 | 79 | static const struct soc_device_attribute rcar_quirks_match[] = { |
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80 | 80 | { |
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.. | .. |
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107 | 107 | of_device_is_compatible(node, "renesas,rcar-gen2-xhci"); |
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108 | 108 | } |
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109 | 109 | |
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110 | | -static int xhci_rcar_is_gen3(struct device *dev) |
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111 | | -{ |
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112 | | - struct device_node *node = dev->of_node; |
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113 | | - |
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114 | | - return of_device_is_compatible(node, "renesas,xhci-r8a7795") || |
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115 | | - of_device_is_compatible(node, "renesas,xhci-r8a7796") || |
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116 | | - of_device_is_compatible(node, "renesas,rcar-gen3-xhci"); |
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117 | | -} |
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118 | | - |
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119 | 110 | void xhci_rcar_start(struct usb_hcd *hcd) |
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120 | 111 | { |
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121 | 112 | u32 temp; |
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.. | .. |
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136 | 127 | void __iomem *regs = hcd->regs; |
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137 | 128 | struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); |
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138 | 129 | const struct firmware *fw; |
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139 | | - int retval, index, j, time; |
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140 | | - int timeout = 10000; |
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| 130 | + int retval, index, j; |
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141 | 131 | u32 data, val, temp; |
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142 | 132 | u32 quirks = 0; |
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143 | 133 | const struct soc_device_attribute *attr; |
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.. | .. |
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156 | 146 | |
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157 | 147 | if (quirks & RCAR_XHCI_FIRMWARE_V2) |
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158 | 148 | firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2; |
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159 | | - else if (quirks & RCAR_XHCI_FIRMWARE_V3) |
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160 | | - firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3; |
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161 | 149 | else |
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162 | 150 | firmware_name = priv->firmware_name; |
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163 | 151 | |
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.. | .. |
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182 | 170 | temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0; |
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183 | 171 | writel(temp, regs + RCAR_USB3_DL_CTRL); |
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184 | 172 | |
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185 | | - for (time = 0; time < timeout; time++) { |
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186 | | - val = readl(regs + RCAR_USB3_DL_CTRL); |
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187 | | - if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0) |
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188 | | - break; |
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189 | | - udelay(1); |
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190 | | - } |
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191 | | - if (time == timeout) { |
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192 | | - retval = -ETIMEDOUT; |
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| 173 | + retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL, |
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| 174 | + val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0), |
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| 175 | + 1, 10000); |
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| 176 | + if (retval < 0) |
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193 | 177 | break; |
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194 | | - } |
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195 | 178 | } |
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196 | 179 | |
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197 | 180 | temp = readl(regs + RCAR_USB3_DL_CTRL); |
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198 | 181 | temp &= ~RCAR_USB3_DL_CTRL_ENABLE; |
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199 | 182 | writel(temp, regs + RCAR_USB3_DL_CTRL); |
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200 | 183 | |
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201 | | - for (time = 0; time < timeout; time++) { |
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202 | | - val = readl(regs + RCAR_USB3_DL_CTRL); |
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203 | | - if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) { |
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204 | | - retval = 0; |
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205 | | - break; |
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206 | | - } |
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207 | | - udelay(1); |
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208 | | - } |
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209 | | - if (time == timeout) |
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210 | | - retval = -ETIMEDOUT; |
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| 184 | + retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL), |
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| 185 | + val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000); |
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211 | 186 | |
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212 | 187 | release_firmware(fw); |
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213 | 188 | |
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.. | .. |
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216 | 191 | |
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217 | 192 | static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd) |
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218 | 193 | { |
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219 | | - int timeout = 1000; |
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| 194 | + int retval; |
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220 | 195 | u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK; |
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221 | 196 | |
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222 | | - while (timeout > 0) { |
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223 | | - val = readl(hcd->regs + RCAR_USB3_AXH_STA); |
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224 | | - if ((val & mask) == mask) |
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225 | | - return true; |
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226 | | - udelay(1); |
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227 | | - timeout--; |
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228 | | - } |
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229 | | - |
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230 | | - return false; |
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| 197 | + retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA, |
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| 198 | + val, (val & mask) == mask, 1, 1000); |
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| 199 | + return !retval; |
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231 | 200 | } |
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232 | 201 | |
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233 | 202 | /* This function needs to initialize a "phy" of usb before */ |
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234 | 203 | int xhci_rcar_init_quirk(struct usb_hcd *hcd) |
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235 | 204 | { |
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236 | | - struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
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237 | | - |
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238 | 205 | /* If hcd->regs is NULL, we don't just call the following function */ |
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239 | 206 | if (!hcd->regs) |
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240 | 207 | return 0; |
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241 | 208 | |
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242 | | - /* |
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243 | | - * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set |
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244 | | - * to 1. However, these SoCs don't support 64-bit address memory |
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245 | | - * pointers. So, this driver clears the AC64 bit of xhci->hcc_params |
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246 | | - * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in |
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247 | | - * xhci_gen_setup(). |
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248 | | - * |
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249 | | - * And, since the firmware/internal CPU control the USBSTS.STS_HALT |
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250 | | - * and the process speed is down when the roothub port enters U3, |
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251 | | - * long delay for the handshake of STS_HALT is neeed in xhci_suspend(). |
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252 | | - */ |
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253 | | - if (xhci_rcar_is_gen2(hcd->self.controller) || |
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254 | | - xhci_rcar_is_gen3(hcd->self.controller)) { |
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255 | | - xhci->quirks |= XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND; |
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256 | | - } |
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257 | | - |
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258 | 209 | if (!xhci_rcar_wait_for_pll_active(hcd)) |
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259 | 210 | return -ETIMEDOUT; |
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260 | 211 | |
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261 | | - xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
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262 | 212 | return xhci_rcar_download_firmware(hcd); |
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263 | 213 | } |
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264 | 214 | |
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