hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
kernel/drivers/usb/host/xhci-rcar.c
....@@ -6,6 +6,7 @@
66 */
77
88 #include <linux/firmware.h>
9
+#include <linux/iopoll.h>
910 #include <linux/module.h>
1011 #include <linux/platform_device.h>
1112 #include <linux/of.h>
....@@ -74,7 +75,6 @@
7475
7576 /* For soc_device_attribute */
7677 #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */
77
-#define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */
7878
7979 static const struct soc_device_attribute rcar_quirks_match[] = {
8080 {
....@@ -107,15 +107,6 @@
107107 of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
108108 }
109109
110
-static int xhci_rcar_is_gen3(struct device *dev)
111
-{
112
- struct device_node *node = dev->of_node;
113
-
114
- return of_device_is_compatible(node, "renesas,xhci-r8a7795") ||
115
- of_device_is_compatible(node, "renesas,xhci-r8a7796") ||
116
- of_device_is_compatible(node, "renesas,rcar-gen3-xhci");
117
-}
118
-
119110 void xhci_rcar_start(struct usb_hcd *hcd)
120111 {
121112 u32 temp;
....@@ -136,8 +127,7 @@
136127 void __iomem *regs = hcd->regs;
137128 struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
138129 const struct firmware *fw;
139
- int retval, index, j, time;
140
- int timeout = 10000;
130
+ int retval, index, j;
141131 u32 data, val, temp;
142132 u32 quirks = 0;
143133 const struct soc_device_attribute *attr;
....@@ -156,8 +146,6 @@
156146
157147 if (quirks & RCAR_XHCI_FIRMWARE_V2)
158148 firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2;
159
- else if (quirks & RCAR_XHCI_FIRMWARE_V3)
160
- firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3;
161149 else
162150 firmware_name = priv->firmware_name;
163151
....@@ -182,32 +170,19 @@
182170 temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
183171 writel(temp, regs + RCAR_USB3_DL_CTRL);
184172
185
- for (time = 0; time < timeout; time++) {
186
- val = readl(regs + RCAR_USB3_DL_CTRL);
187
- if ((val & RCAR_USB3_DL_CTRL_FW_SET_DATA0) == 0)
188
- break;
189
- udelay(1);
190
- }
191
- if (time == timeout) {
192
- retval = -ETIMEDOUT;
173
+ retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
174
+ val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
175
+ 1, 10000);
176
+ if (retval < 0)
193177 break;
194
- }
195178 }
196179
197180 temp = readl(regs + RCAR_USB3_DL_CTRL);
198181 temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
199182 writel(temp, regs + RCAR_USB3_DL_CTRL);
200183
201
- for (time = 0; time < timeout; time++) {
202
- val = readl(regs + RCAR_USB3_DL_CTRL);
203
- if (val & RCAR_USB3_DL_CTRL_FW_SUCCESS) {
204
- retval = 0;
205
- break;
206
- }
207
- udelay(1);
208
- }
209
- if (time == timeout)
210
- retval = -ETIMEDOUT;
184
+ retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
185
+ val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
211186
212187 release_firmware(fw);
213188
....@@ -216,49 +191,24 @@
216191
217192 static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
218193 {
219
- int timeout = 1000;
194
+ int retval;
220195 u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
221196
222
- while (timeout > 0) {
223
- val = readl(hcd->regs + RCAR_USB3_AXH_STA);
224
- if ((val & mask) == mask)
225
- return true;
226
- udelay(1);
227
- timeout--;
228
- }
229
-
230
- return false;
197
+ retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
198
+ val, (val & mask) == mask, 1, 1000);
199
+ return !retval;
231200 }
232201
233202 /* This function needs to initialize a "phy" of usb before */
234203 int xhci_rcar_init_quirk(struct usb_hcd *hcd)
235204 {
236
- struct xhci_hcd *xhci = hcd_to_xhci(hcd);
237
-
238205 /* If hcd->regs is NULL, we don't just call the following function */
239206 if (!hcd->regs)
240207 return 0;
241208
242
- /*
243
- * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
244
- * to 1. However, these SoCs don't support 64-bit address memory
245
- * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
246
- * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
247
- * xhci_gen_setup().
248
- *
249
- * And, since the firmware/internal CPU control the USBSTS.STS_HALT
250
- * and the process speed is down when the roothub port enters U3,
251
- * long delay for the handshake of STS_HALT is neeed in xhci_suspend().
252
- */
253
- if (xhci_rcar_is_gen2(hcd->self.controller) ||
254
- xhci_rcar_is_gen3(hcd->self.controller)) {
255
- xhci->quirks |= XHCI_NO_64BIT_SUPPORT | XHCI_SLOW_SUSPEND;
256
- }
257
-
258209 if (!xhci_rcar_wait_for_pll_active(hcd))
259210 return -ETIMEDOUT;
260211
261
- xhci->quirks |= XHCI_TRUST_TX_LENGTH;
262212 return xhci_rcar_download_firmware(hcd);
263213 }
264214