hc
2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d
kernel/drivers/pwm/pwm-bcm-kona.c
....@@ -45,25 +45,25 @@
4545 * high or low depending on its state at that exact instant.
4646 */
4747
48
-#define PWM_CONTROL_OFFSET (0x00000000)
48
+#define PWM_CONTROL_OFFSET 0x00000000
4949 #define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
5050 #define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
5151 #define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
5252 #define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
5353
54
-#define PRESCALE_OFFSET (0x00000004)
54
+#define PRESCALE_OFFSET 0x00000004
5555 #define PRESCALE_SHIFT(chan) ((chan) << 2)
5656 #define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
57
-#define PRESCALE_MIN (0x00000000)
58
-#define PRESCALE_MAX (0x00000007)
57
+#define PRESCALE_MIN 0x00000000
58
+#define PRESCALE_MAX 0x00000007
5959
6060 #define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
61
-#define PERIOD_COUNT_MIN (0x00000002)
62
-#define PERIOD_COUNT_MAX (0x00ffffff)
61
+#define PERIOD_COUNT_MIN 0x00000002
62
+#define PERIOD_COUNT_MAX 0x00ffffff
6363
6464 #define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
65
-#define DUTY_CYCLE_HIGH_MIN (0x00000000)
66
-#define DUTY_CYCLE_HIGH_MAX (0x00ffffff)
65
+#define DUTY_CYCLE_HIGH_MIN 0x00000000
66
+#define DUTY_CYCLE_HIGH_MAX 0x00ffffff
6767
6868 struct kona_pwmc {
6969 struct pwm_chip chip;
....@@ -138,7 +138,7 @@
138138 dc = div64_u64(val, div);
139139
140140 /* If duty_ns or period_ns are not achievable then return */
141
- if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN)
141
+ if (pc < PERIOD_COUNT_MIN)
142142 return -EINVAL;
143143
144144 /* If pc and dc are in bounds, the calculation is done */