修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c
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@@ -6,7 +6,7 @@
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  * GPL LICENSE SUMMARY
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  *
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  * Copyright(c) 2017 Intel Deutschland GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2021 Intel Corporation
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  *
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  * This program is free software; you can redistribute it and/or modify
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  * it under the terms of version 2 of the GNU General Public License as
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@@ -20,7 +20,7 @@
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  * BSD LICENSE
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  *
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  * Copyright(c) 2017 Intel Deutschland GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2020 Intel Corporation
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  * All rights reserved.
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  *
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  * Redistribution and use in source and binary forms, with or without
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@@ -57,10 +57,60 @@
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 #include "internal.h"
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 #include "iwl-prph.h"
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+static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
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+						    size_t size,
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+						    dma_addr_t *phys,
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+						    int depth)
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+{
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+	void *result;
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+
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+	if (WARN(depth > 2,
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+		 "failed to allocate DMA memory not crossing 2^32 boundary"))
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+		return NULL;
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+
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+	result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
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+
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+	if (!result)
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+		return NULL;
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+
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+	if (unlikely(iwl_txq_crosses_4g_boundary(*phys, size))) {
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+		void *old = result;
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+		dma_addr_t oldphys = *phys;
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+
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+		result = _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size,
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+								phys,
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+								depth + 1);
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+		dma_free_coherent(trans->dev, size, old, oldphys);
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+	}
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+
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+	return result;
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+}
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+
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+static void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
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+						   size_t size,
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+						   dma_addr_t *phys)
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+{
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+	return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
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+}
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+
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+int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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+				 const void *data, u32 len,
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+				 struct iwl_dram_data *dram)
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+{
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+	dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
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+							    &dram->physical);
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+	if (!dram->block)
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+		return -ENOMEM;
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+
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+	dram->size = len;
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+	memcpy(dram->block, data, len);
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+
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+	return 0;
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+}
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+
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 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
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 {
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-	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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-	struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
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+	struct iwl_self_init_dram *dram = &trans->init_dram;
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 	int i;
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 	if (!dram->paging) {
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@@ -83,8 +133,7 @@
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 			 const struct fw_img *fw,
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 			 struct iwl_context_info_dram *ctxt_dram)
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 {
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-	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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-	struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
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+	struct iwl_self_init_dram *dram = &trans->init_dram;
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 	int i, ret, lmac_cnt, umac_cnt, paging_cnt;
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 	if (WARN(dram->paging,
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@@ -107,7 +156,8 @@
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 	/* initialize lmac sections */
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 	for (i = 0; i < lmac_cnt; i++) {
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-		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
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+		ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[i].data,
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+						   fw->sec[i].len,
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 						   &dram->fw[dram->fw_cnt]);
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 		if (ret)
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 			return ret;
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@@ -120,7 +170,8 @@
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 	for (i = 0; i < umac_cnt; i++) {
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 		/* access FW with +1 to make up for lmac separator */
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 		ret = iwl_pcie_ctxt_info_alloc_dma(trans,
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-						   &fw->sec[dram->fw_cnt + 1],
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+						   fw->sec[dram->fw_cnt + 1].data,
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+						   fw->sec[dram->fw_cnt + 1].len,
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 						   &dram->fw[dram->fw_cnt]);
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 		if (ret)
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 			return ret;
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@@ -143,7 +194,8 @@
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 		/* access FW with +2 to make up for lmac & umac separators */
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 		int fw_idx = dram->fw_cnt + i + 2;
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-		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
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+		ret = iwl_pcie_ctxt_info_alloc_dma(trans, fw->sec[fw_idx].data,
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+						   fw->sec[fw_idx].len,
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 						   &dram->paging[i]);
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 		if (ret)
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 			return ret;
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@@ -162,14 +214,17 @@
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 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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 	struct iwl_context_info *ctxt_info;
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 	struct iwl_context_info_rbd_cfg *rx_cfg;
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-	u32 control_flags = 0;
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+	u32 control_flags = 0, rb_size;
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+	dma_addr_t phys;
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 	int ret;
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-	ctxt_info = dma_alloc_coherent(trans->dev, sizeof(*ctxt_info),
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-				       &trans_pcie->ctxt_info_dma_addr,
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-				       GFP_KERNEL);
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+	ctxt_info = iwl_pcie_ctxt_info_dma_alloc_coherent(trans,
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+							  sizeof(*ctxt_info),
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+							  &phys);
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 	if (!ctxt_info)
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 		return -ENOMEM;
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+
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+	trans_pcie->ctxt_info_dma_addr = phys;
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 	ctxt_info->version.version = 0;
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 	ctxt_info->version.mac_id =
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@@ -177,11 +232,30 @@
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 	/* size is in DWs */
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 	ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
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-	BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
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-	control_flags = IWL_CTXT_INFO_RB_SIZE_4K |
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-			IWL_CTXT_INFO_TFD_FORMAT_LONG |
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-			RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
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-			IWL_CTXT_INFO_RB_CB_SIZE_POS;
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+	switch (trans_pcie->rx_buf_size) {
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+	case IWL_AMSDU_2K:
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+		rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
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+		break;
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+	case IWL_AMSDU_4K:
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+		rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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+		break;
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+	case IWL_AMSDU_8K:
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+		rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
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+		break;
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+	case IWL_AMSDU_12K:
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+		rb_size = IWL_CTXT_INFO_RB_SIZE_12K;
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+		break;
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+	default:
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+		WARN_ON(1);
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+		rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
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+	}
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+
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+	WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
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+	control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
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+	control_flags |=
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+		u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
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+				IWL_CTXT_INFO_RB_CB_SIZE);
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+	control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
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 	ctxt_info->control.control_flags = cpu_to_le32(control_flags);
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 	/* initialize RX default queue */
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@@ -192,9 +266,9 @@
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 	/* initialize TX command queue */
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 	ctxt_info->hcmd_cfg.cmd_queue_addr =
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-		cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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+		cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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 	ctxt_info->hcmd_cfg.cmd_queue_size =
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-		TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS);
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+		TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
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 	/* allocate ucode sections in dram and set addresses */
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 	ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
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@@ -209,12 +283,11 @@
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 	iwl_enable_fw_load_int_ctx_info(trans);
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 	/* Configure debug, if exists */
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-	if (trans->dbg_dest_tlv)
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+	if (iwl_pcie_dbg_on(trans))
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 		iwl_pcie_apply_destination(trans);
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 	/* kick FW self load */
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 	iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
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-	iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
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 	/* Context info will be released upon alive or failure to get one */
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