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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/net/wireless/intel/iwlwifi/iwl-prph.h
....@@ -5,10 +5,9 @@
55  *
66  * GPL LICENSE SUMMARY
77  *
8
- * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9
- * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
8
+ * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
109  * Copyright(c) 2016        Intel Deutschland GmbH
11
- * Copyright (C) 2018 Intel Corporation
10
+ * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
1211  *
1312  * This program is free software; you can redistribute it and/or modify
1413  * it under the terms of version 2 of the GNU General Public License as
....@@ -19,11 +18,6 @@
1918  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
2019  * General Public License for more details.
2120  *
22
- * You should have received a copy of the GNU General Public License
23
- * along with this program; if not, write to the Free Software
24
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25
- * USA
26
- *
2721  * The full GNU General Public License is included in this distribution
2822  * in the file called COPYING.
2923  *
....@@ -33,10 +27,9 @@
3327  *
3428  * BSD LICENSE
3529  *
36
- * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37
- * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
30
+ * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
3831  * Copyright(c) 2016        Intel Deutschland GmbH
39
- * Copyright (C) 2018 Intel Corporation
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+ * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
4033  * All rights reserved.
4134  *
4235  * Redistribution and use in source and binary forms, with or without
....@@ -331,6 +324,7 @@
331324 #define RXF_SIZE_BYTE_CND_POS		(7)
332325 #define RXF_SIZE_BYTE_CNT_MSK		(0x3ff << RXF_SIZE_BYTE_CND_POS)
333326 #define RXF_DIFF_FROM_PREV		(0x200)
327
+#define RXF2C_DIFF_FROM_PREV		(0x4e00)
334328 
335329 #define RXF_LD_FENCE_OFFSET_ADDR	(0xa00c10)
336330 #define RXF_FIFO_RD_FENCE_ADDR		(0xa00c0c)
....@@ -361,18 +355,43 @@
361355 #define RADIO_RSP_ADDR_POS		(6)
362356 #define RADIO_RSP_RD_CMD		(3)
363357 
358
+/* LTR control (Qu only) */
359
+#define HPM_MAC_LTR_CSR			0xa0348c
360
+#define HPM_MAC_LRT_ENABLE_ALL		0xf
361
+/* also uses CSR_LTR_* for values */
362
+#define HPM_UMAC_LTR			0xa03480
363
+
364364 /* FW monitor */
365365 #define MON_BUFF_SAMPLE_CTL		(0xa03c00)
366
-#define MON_BUFF_BASE_ADDR		(0xa03c3c)
366
+#define MON_BUFF_BASE_ADDR		(0xa03c1c)
367367 #define MON_BUFF_END_ADDR		(0xa03c40)
368368 #define MON_BUFF_WRPTR			(0xa03c44)
369369 #define MON_BUFF_CYCLE_CNT		(0xa03c48)
370
+/* FW monitor family 8000 and on */
371
+#define MON_BUFF_BASE_ADDR_VER2		(0xa03c1c)
372
+#define MON_BUFF_END_ADDR_VER2		(0xa03c20)
373
+#define MON_BUFF_WRPTR_VER2		(0xa03c24)
374
+#define MON_BUFF_CYCLE_CNT_VER2		(0xa03c28)
375
+#define MON_BUFF_SHIFT_VER2		(0x8)
376
+/* FW monitor familiy AX210 and on */
377
+#define DBGC_CUR_DBGBUF_BASE_ADDR_LSB		(0xd03c20)
378
+#define DBGC_CUR_DBGBUF_BASE_ADDR_MSB		(0xd03c24)
379
+#define DBGC_CUR_DBGBUF_STATUS			(0xd03c1c)
380
+#define DBGC_DBGBUF_WRAP_AROUND			(0xd03c2c)
381
+#define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK	(0x00ffffff)
382
+#define DBGC_CUR_DBGBUF_STATUS_IDX_MSK		(0x0f000000)
370383 
371384 #define MON_DMARB_RD_CTL_ADDR		(0xa03c60)
372385 #define MON_DMARB_RD_DATA_ADDR		(0xa03c5c)
373386 
374387 #define DBGC_IN_SAMPLE			(0xa03c00)
375388 #define DBGC_OUT_CTRL			(0xa03c0c)
389
+
390
+/* M2S registers */
391
+#define LDBG_M2S_BUF_WPTR			(0xa0476c)
392
+#define LDBG_M2S_BUF_WRAP_CNT			(0xa04774)
393
+#define LDBG_M2S_BUF_WPTR_VAL_MSK		(0x000fffff)
394
+#define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK		(0x000fffff)
376395 
377396 /* enable the ID buf for read */
378397 #define WFPM_PS_CTL_CLR			0xA0300C
....@@ -388,25 +407,30 @@
388407 	WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK	= 0x80000000,
389408 };
390409 
391
-#define AUX_MISC_REG			0xA200B0
410
+#define CNVI_AUX_MISC_CHIP				0xA200B0
411
+#define CNVR_AUX_MISC_CHIP				0xA2B800
412
+#define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM		0xA29890
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+#define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR	0xA29938
414
+
392415 enum {
393416 	HW_STEP_LOCATION_BITS = 24,
394417 };
395418 
396
-#define AUX_MISC_MASTER1_EN		0xA20818
397
-enum aux_misc_master1_en {
398
-	AUX_MISC_MASTER1_EN_SBE_MSK	= 0x1,
399
-};
400
-
401
-#define AUX_MISC_MASTER1_SMPHR_STATUS	0xA20800
402
-#define RSA_ENABLE			0xA24B08
403419 #define PREG_AUX_BUS_WPROT_0		0xA04CC0
404
-#define PREG_PRPH_WPROT_0		0xA04CE0
420
+
421
+/* device family 9000 WPROT register */
422
+#define PREG_PRPH_WPROT_9000		0xA04CE0
423
+/* device family 22000 WPROT register */
424
+#define PREG_PRPH_WPROT_22000		0xA04D00
425
+
405426 #define SB_CPU_1_STATUS			0xA01E30
406427 #define SB_CPU_2_STATUS			0xA01E34
407428 #define UMAG_SB_CPU_1_STATUS		0xA038C0
408429 #define UMAG_SB_CPU_2_STATUS		0xA038C4
409430 #define UMAG_GEN_HW_STATUS		0xA038C8
431
+#define UREG_UMAC_CURRENT_PC		0xa05c18
432
+#define UREG_LMAC1_CURRENT_PC		0xa05c1c
433
+#define UREG_LMAC2_CURRENT_PC		0xa05c20
410434 
411435 /* For UMAG_GEN_HW_STATUS reg check */
412436 enum {
....@@ -432,4 +456,27 @@
432456 #define HPM_DEBUG			0xA03440
433457 #define PERSISTENCE_BIT			BIT(12)
434458 #define PREG_WFPM_ACCESS		BIT(12)
459
+
460
+#define HPM_HIPM_GEN_CFG			0xA03458
461
+#define HPM_HIPM_GEN_CFG_CR_PG_EN		BIT(0)
462
+#define HPM_HIPM_GEN_CFG_CR_SLP_EN		BIT(1)
463
+#define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE	BIT(10)
464
+
465
+#define UREG_DOORBELL_TO_ISR6		0xA05C04
466
+#define UREG_DOORBELL_TO_ISR6_NMI_BIT	BIT(0)
467
+#define UREG_DOORBELL_TO_ISR6_SUSPEND	BIT(18)
468
+#define UREG_DOORBELL_TO_ISR6_RESUME	BIT(19)
469
+#define UREG_DOORBELL_TO_ISR6_PNVM	BIT(20)
470
+
471
+#define FSEQ_ERROR_CODE			0xA340C8
472
+#define FSEQ_TOP_INIT_VERSION		0xA34038
473
+#define FSEQ_CNVIO_INIT_VERSION		0xA3403C
474
+#define FSEQ_OTP_VERSION		0xA340FC
475
+#define FSEQ_TOP_CONTENT_VERSION	0xA340F4
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+#define FSEQ_ALIVE_TOKEN		0xA340F0
477
+#define FSEQ_CNVI_ID			0xA3408C
478
+#define FSEQ_CNVR_ID			0xA34090
479
+
480
+#define IWL_D3_SLEEP_STATUS_SUSPEND	0xD3
481
+#define IWL_D3_SLEEP_STATUS_RESUME	0xD0
435482 #endif				/* __iwl_prph_h__ */