修改led为gpio

hc

2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d

 kernel/drivers/net/wireless/intel/iwlwifi/iwl-context-info.h
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@@ -6,7 +6,7 @@
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  * GPL LICENSE SUMMARY
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  *
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  * Copyright(c) 2017 Intel Deutschland GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2020 Intel Corporation
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  *
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  * This program is free software; you can redistribute it and/or modify
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  * it under the terms of version 2 of the GNU General Public License as
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@@ -20,7 +20,7 @@
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  * BSD LICENSE
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  *
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  * Copyright(c) 2017 Intel Deutschland GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2020 Intel Corporation
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  * All rights reserved.
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  *
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  * Redistribution and use in source and binary forms, with or without
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@@ -64,20 +64,41 @@
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  *	the init done for driver command that configures several system modes
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  * @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
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  * @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
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- * @IWL_CTXT_INFO_RB_SIZE_4K: Use 4K RB size (the default is 2K)
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- * @IWL_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
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+ * @IWL_CTXT_INFO_RB_CB_SIZE: mask of the RBD Cyclic Buffer Size
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  *	exponent, the actual size is 2**value, valid sizes are 8-2048.
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  *	The value is four bits long. Maximum valid exponent is 12
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  * @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
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  *	default is short format - not supported by the driver)
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+ * @IWL_CTXT_INFO_RB_SIZE: RB size mask
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+ *	(values are IWL_CTXT_INFO_RB_SIZE_*K)
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+ * @IWL_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
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+ * @IWL_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
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  */
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 enum iwl_context_info_flags {
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-	IWL_CTXT_INFO_AUTO_FUNC_INIT	= BIT(0),
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-	IWL_CTXT_INFO_EARLY_DEBUG	= BIT(1),
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-	IWL_CTXT_INFO_ENABLE_CDMP	= BIT(2),
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-	IWL_CTXT_INFO_RB_SIZE_4K	= BIT(3),
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-	IWL_CTXT_INFO_RB_CB_SIZE_POS	= 4,
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-	IWL_CTXT_INFO_TFD_FORMAT_LONG	= BIT(8),
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+	IWL_CTXT_INFO_AUTO_FUNC_INIT	= 0x0001,
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+	IWL_CTXT_INFO_EARLY_DEBUG	= 0x0002,
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+	IWL_CTXT_INFO_ENABLE_CDMP	= 0x0004,
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+	IWL_CTXT_INFO_RB_CB_SIZE	= 0x00f0,
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+	IWL_CTXT_INFO_TFD_FORMAT_LONG	= 0x0100,
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+	IWL_CTXT_INFO_RB_SIZE		= 0x1e00,
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+	IWL_CTXT_INFO_RB_SIZE_1K	= 0x1,
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+	IWL_CTXT_INFO_RB_SIZE_2K	= 0x2,
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+	IWL_CTXT_INFO_RB_SIZE_4K	= 0x4,
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+	IWL_CTXT_INFO_RB_SIZE_8K	= 0x8,
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+	IWL_CTXT_INFO_RB_SIZE_12K	= 0x9,
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+	IWL_CTXT_INFO_RB_SIZE_16K	= 0xa,
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+	IWL_CTXT_INFO_RB_SIZE_20K	= 0xb,
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+	IWL_CTXT_INFO_RB_SIZE_24K	= 0xc,
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+	IWL_CTXT_INFO_RB_SIZE_28K	= 0xd,
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+	IWL_CTXT_INFO_RB_SIZE_32K	= 0xe,
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 };
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 /*
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@@ -204,5 +225,8 @@
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 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
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 			 const struct fw_img *fw,
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 			 struct iwl_context_info_dram *ctxt_dram);
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+int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
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+				 const void *data, u32 len,
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+				 struct iwl_dram_data *dram);
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 #endif /* __iwl_context_info_file_h__ */