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2024-10-12 a5969cabbb4660eab42b6ef0412cbbd1200cf14d 
 kernel/drivers/net/wireless/intel/iwlwifi/iwl-config.h
....@@ -5,9 +5,8 @@
55  *
66  * GPL LICENSE SUMMARY
77  *
8
- * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
98  * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
10
- * Copyright(c) 2018 Intel Corporation
9
+ * Copyright(c) 2007 - 2014, 2018 - 2020 Intel Corporation
1110  *
1211  * This program is free software; you can redistribute it and/or modify
1312  * it under the terms of version 2 of the GNU General Public License as
....@@ -18,11 +17,6 @@
1817  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
1918  * General Public License for more details.
2019  *
21
- * You should have received a copy of the GNU General Public License
22
- * along with this program; if not, write to the Free Software
23
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24
- * USA
25
- *
2620  * The full GNU General Public License is included in this distribution
2721  * in the file called COPYING.
2822  *
....@@ -32,9 +26,8 @@
3226  *
3327  * BSD LICENSE
3428  *
35
- * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
3629  * Copyright (C) 2016 - 2017 Intel Deutschland GmbH
37
- * Copyright(c) 2018 Intel Corporation
30
+ * Copyright(c) 2005 - 2014, 2018 - 2020 Intel Corporation
3831  * All rights reserved.
3932  *
4033  * Redistribution and use in source and binary forms, with or without
....@@ -93,7 +86,7 @@
9386 	IWL_DEVICE_FAMILY_8000,
9487 	IWL_DEVICE_FAMILY_9000,
9588 	IWL_DEVICE_FAMILY_22000,
96
-	IWL_DEVICE_FAMILY_22560,
89
+	IWL_DEVICE_FAMILY_AX210,
9790 };
9891 
9992 /*
....@@ -165,7 +158,8 @@
165158 		!!((mask) & ANT_C);
166159 }
167160 
168
-/*
161
+/**
162
+ * struct iwl_base_params - params not likely to change within a device family
169163  * @max_ll_items: max number of OTP blocks
170164  * @shadow_ram_support: shadow support for OTP memory
171165  * @led_compensation: compensate on the led on/off time per HW according
....@@ -270,11 +264,9 @@
270264 #define EEPROM_REGULATORY_BAND_NO_HT40		0
271265 
272266 /* lower blocks contain EEPROM image and calibration data */
273
-#define OTP_LOW_IMAGE_SIZE		(2 * 512 * sizeof(u16)) /* 2 KB */
274
-#define OTP_LOW_IMAGE_SIZE_FAMILY_7000	(16 * 512 * sizeof(u16)) /* 16 KB */
275
-#define OTP_LOW_IMAGE_SIZE_FAMILY_8000	(32 * 512 * sizeof(u16)) /* 32 KB */
276
-#define OTP_LOW_IMAGE_SIZE_FAMILY_9000	OTP_LOW_IMAGE_SIZE_FAMILY_8000
277
-#define OTP_LOW_IMAGE_SIZE_FAMILY_22000	OTP_LOW_IMAGE_SIZE_FAMILY_9000
267
+#define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
268
+#define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
269
+#define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
278270 
279271 struct iwl_eeprom_params {
280272 	const u8 regulatory_bands[7];
....@@ -290,62 +282,80 @@
290282 	u32 backoff;
291283 };
292284 
285
+enum iwl_cfg_trans_ltr_delay {
286
+	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
287
+	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
288
+	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
289
+	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
290
+};
291
+
293292 /**
294
- * struct iwl_csr_params
293
+ * struct iwl_cfg_trans - information needed to start the trans
295294  *
296
- * @flag_sw_reset: reset the device
297
- * @flag_mac_clock_ready:
298
- *	Indicates MAC (ucode processor, etc.) is powered up and can run.
299
- *	Internal resources are accessible.
300
- *	NOTE:  This does not indicate that the processor is actually running.
301
- *	NOTE:  This does not indicate that device has completed
302
- *	       init or post-power-down restore of internal SRAM memory.
303
- *	       Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
304
- *	       SRAM is restored and uCode is in normal operation mode.
305
- *	       This note is relevant only for pre 5xxx devices.
306
- *	NOTE:  After device reset, this bit remains "0" until host sets
307
- *	       INIT_DONE
308
- * @flag_init_done: Host sets this to put device into fully operational
309
- *	D0 power mode. Host resets this after SW_RESET to put device into
310
- *	low power mode.
311
- * @flag_mac_access_req: Host sets this to request and maintain MAC wakeup,
312
- *	to allow host access to device-internal resources. Host must wait for
313
- *	mac_clock_ready (and !GOING_TO_SLEEP) before accessing non-CSR device
314
- *	registers.
315
- * @flag_val_mac_access_en: mac access is enabled
316
- * @flag_master_dis: disable master
317
- * @flag_stop_master: stop master
318
- * @addr_sw_reset: address for resetting the device
319
- * @mac_addr0_otp: first part of MAC address from OTP
320
- * @mac_addr1_otp: second part of MAC address from OTP
321
- * @mac_addr0_strap: first part of MAC address from strap
322
- * @mac_addr1_strap: second part of MAC address from strap
295
+ * These values are specific to the device ID and do not change when
296
+ * multiple configs are used for a single device ID.  They values are
297
+ * used, among other things, to boot the NIC so that the HW REV or
298
+ * RFID can be read before deciding the remaining parameters to use.
299
+ *
300
+ * @base_params: pointer to basic parameters
301
+ * @csr: csr flags and addresses that are different across devices
302
+ * @device_family: the device family
303
+ * @umac_prph_offset: offset to add to UMAC periphery address
304
+ * @xtal_latency: power up latency to get the xtal stabilized
305
+ * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
306
+ * @rf_id: need to read rf_id to determine the firmware image
307
+ * @use_tfh: use TFH
308
+ * @gen2: 22000 and on transport operation
309
+ * @mq_rx_supported: multi-queue rx support
310
+ * @integrated: discrete or integrated
311
+ * @low_latency_xtal: use the low latency xtal if supported
312
+ * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay.
323313  */
324
-struct iwl_csr_params {
325
-	u8 flag_sw_reset;
326
-	u8 flag_mac_clock_ready;
327
-	u8 flag_init_done;
328
-	u8 flag_mac_access_req;
329
-	u8 flag_val_mac_access_en;
330
-	u8 flag_master_dis;
331
-	u8 flag_stop_master;
332
-	u8 addr_sw_reset;
333
-	u32 mac_addr0_otp;
334
-	u32 mac_addr1_otp;
335
-	u32 mac_addr0_strap;
336
-	u32 mac_addr1_strap;
314
+struct iwl_cfg_trans_params {
315
+	const struct iwl_base_params *base_params;
316
+	enum iwl_device_family device_family;
317
+	u32 umac_prph_offset;
318
+	u32 xtal_latency;
319
+	u32 extra_phy_cfg_flags;
320
+	u32 rf_id:1,
321
+	    use_tfh:1,
322
+	    gen2:1,
323
+	    mq_rx_supported:1,
324
+	    integrated:1,
325
+	    low_latency_xtal:1,
326
+	    bisr_workaround:1,
327
+	    ltr_delay:2;
328
+};
329
+
330
+/**
331
+ * struct iwl_fw_mon_reg - FW monitor register info
332
+ * @addr: register address
333
+ * @mask: register mask
334
+ */
335
+struct iwl_fw_mon_reg {
336
+	u32 addr;
337
+	u32 mask;
338
+};
339
+
340
+/**
341
+ * struct iwl_fw_mon_regs - FW monitor registers
342
+ * @write_ptr: write pointer register
343
+ * @cycle_cnt: cycle count register
344
+ * @cur_frag: current fragment in use
345
+ */
346
+struct iwl_fw_mon_regs {
347
+	struct iwl_fw_mon_reg write_ptr;
348
+	struct iwl_fw_mon_reg cycle_cnt;
349
+	struct iwl_fw_mon_reg cur_frag;
337350 };
338351 
339352 /**
340353  * struct iwl_cfg
354
+ * @trans: the trans-specific configuration part
341355  * @name: Official name of the device
342356  * @fw_name_pre: Firmware filename prefix. The api version and extension
343357  *	(.ucode) will be added to filename before loading from disk. The
344358  *	filename is constructed as fw_name_pre<api>.ucode.
345
- * @fw_name_pre_b_or_c_step: same as @fw_name_pre, only for b or c steps
346
- *	(if supported)
347
- * @fw_name_pre_rf_next_step: same as @fw_name_pre_b_or_c_step, only for rf
348
- *	next step. Supported only in integrated solutions.
349359  * @ucode_api_max: Highest version of uCode API supported by driver.
350360  * @ucode_api_min: Lowest version of uCode API supported by driver.
351361  * @max_inst_size: The maximal length of the fw inst section (only DVM)
....@@ -356,20 +366,18 @@
356366  * @nvm_ver: NVM version
357367  * @nvm_calib_ver: NVM calibration version
358368  * @lib: pointer to the lib ops
359
- * @base_params: pointer to basic parameters
360369  * @ht_params: point to ht parameters
361370  * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
362371  * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
372
+ * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
363373  * @internal_wimax_coex: internal wifi/wimax combo device
364374  * @high_temp: Is this NIC is designated to be in high temperature.
365375  * @host_interrupt_operation_mode: device needs host interrupt operation
366376  *	mode set
367377  * @nvm_hw_section_num: the ID of the HW NVM section
368378  * @mac_addr_from_csr: read HW address from CSR registers
369
- * @features: hw features, any combination of feature_whitelist
379
+ * @features: hw features, any combination of feature_passlist
370380  * @pwr_tx_backoffs: translation table between power limits and backoffs
371
- * @csr: csr flags and addresses that are different across devices
372
- * @max_rx_agg_size: max RX aggregation size of the ADDBA request/response
373381  * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response
374382  * @max_ht_ampdu_factor: the exponent of the max length of A-MPDU that the
375383  *	station can receive in HT
....@@ -381,34 +389,34 @@
381389  * @dccm2_len: length of the second DCCM
382390  * @smem_offset: offset from which the SMEM begins
383391  * @smem_len: the length of SMEM
384
- * @mq_rx_supported: multi-queue rx support
385392  * @vht_mu_mimo_supported: VHT MU-MIMO support
386
- * @rf_id: need to read rf_id to determine the firmware image
387
- * @integrated: discrete or integrated
388
- * @gen2: 22000 and on transport operation
389393  * @cdb: CDB support
390394  * @nvm_type: see &enum iwl_nvm_type
395
+ * @d3_debug_data_base_addr: base address where D3 debug data is stored
396
+ * @d3_debug_data_length: length of the D3 debug data
397
+ * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
398
+ * @min_txq_size: minimum number of slots required in a TX queue
399
+ * @uhb_supported: ultra high band channels supported
400
+ * @min_256_ba_txq_size: minimum number of slots required in a TX queue which
401
+ *	supports 256 BA aggregation
402
+ * @num_rbds: number of receive buffer descriptors to use
403
+ *	(only used for multi-queue capable devices)
391404  *
392405  * We enable the driver to be backward compatible wrt. hardware features.
393406  * API differences in uCode shouldn't be handled here but through TLVs
394407  * and/or the uCode API version instead.
395408  */
396409 struct iwl_cfg {
410
+	struct iwl_cfg_trans_params trans;
397411 	/* params specific to an individual device within a device family */
398412 	const char *name;
399413 	const char *fw_name_pre;
400
-	const char *fw_name_pre_b_or_c_step;
401
-	const char *fw_name_pre_rf_next_step;
402
-	/* params not likely to change within a device family */
403
-	const struct iwl_base_params *base_params;
404414 	/* params likely to change within a device family */
405415 	const struct iwl_ht_params *ht_params;
406416 	const struct iwl_eeprom_params *eeprom_params;
407417 	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
408418 	const char *default_nvm_file_C_step;
409419 	const struct iwl_tt_params *thermal_params;
410
-	const struct iwl_csr_params *csr;
411
-	enum iwl_device_family device_family;
412420 	enum iwl_led_mode led_mode;
413421 	enum iwl_nvm_type nvm_type;
414422 	u32 max_data_size;
....@@ -420,10 +428,10 @@
420428 	u32 dccm2_len;
421429 	u32 smem_offset;
422430 	u32 smem_len;
423
-	u32 soc_latency;
424431 	u16 nvm_ver;
425432 	u16 nvm_calib_ver;
426433 	u32 rx_with_siso_diversity:1,
434
+	    tx_with_siso_diversity:1,
427435 	    bt_shared_single_ant:1,
428436 	    internal_wimax_coex:1,
429437 	    host_interrupt_operation_mode:1,
....@@ -432,61 +440,121 @@
432440 	    lp_xtal_workaround:1,
433441 	    disable_dummy_notification:1,
434442 	    apmg_not_supported:1,
435
-	    mq_rx_supported:1,
436443 	    vht_mu_mimo_supported:1,
437
-	    rf_id:1,
438
-	    integrated:1,
439
-	    use_tfh:1,
440
-	    gen2:1,
441444 	    cdb:1,
442
-	    dbgc_supported:1;
445
+	    dbgc_supported:1,
446
+	    uhb_supported:1;
443447 	u8 valid_tx_ant;
444448 	u8 valid_rx_ant;
445449 	u8 non_shared_ant;
446450 	u8 nvm_hw_section_num;
447
-	u8 max_rx_agg_size;
448451 	u8 max_tx_agg_size;
449452 	u8 max_ht_ampdu_exponent;
450453 	u8 max_vht_ampdu_exponent;
451454 	u8 ucode_api_max;
452455 	u8 ucode_api_min;
456
+	u16 num_rbds;
453457 	u32 min_umac_error_event_table;
454
-	u32 extra_phy_cfg_flags;
458
+	u32 d3_debug_data_base_addr;
459
+	u32 d3_debug_data_length;
460
+	u32 min_txq_size;
461
+	u32 gp2_reg_addr;
462
+	u32 min_256_ba_txq_size;
463
+	const struct iwl_fw_mon_regs mon_dram_regs;
464
+	const struct iwl_fw_mon_regs mon_smem_regs;
455465 };
456466 
457
-static const struct iwl_csr_params iwl_csr_v1 = {
458
-	.flag_mac_clock_ready = 0,
459
-	.flag_val_mac_access_en = 0,
460
-	.flag_init_done = 2,
461
-	.flag_mac_access_req = 3,
462
-	.flag_sw_reset = 7,
463
-	.flag_master_dis = 8,
464
-	.flag_stop_master = 9,
465
-	.addr_sw_reset = (CSR_BASE + 0x020),
466
-	.mac_addr0_otp = 0x380,
467
-	.mac_addr1_otp = 0x384,
468
-	.mac_addr0_strap = 0x388,
469
-	.mac_addr1_strap = 0x38C
470
-};
467
+#define IWL_CFG_ANY (~0)
471468 
472
-static const struct iwl_csr_params iwl_csr_v2 = {
473
-	.flag_init_done = 6,
474
-	.flag_mac_clock_ready = 20,
475
-	.flag_val_mac_access_en = 20,
476
-	.flag_mac_access_req = 21,
477
-	.flag_master_dis = 28,
478
-	.flag_stop_master = 29,
479
-	.flag_sw_reset = 31,
480
-	.addr_sw_reset = (CSR_BASE + 0x024),
481
-	.mac_addr0_otp = 0x30,
482
-	.mac_addr1_otp = 0x34,
483
-	.mac_addr0_strap = 0x38,
484
-	.mac_addr1_strap = 0x3C
469
+#define IWL_CFG_MAC_TYPE_PU		0x31
470
+#define IWL_CFG_MAC_TYPE_PNJ		0x32
471
+#define IWL_CFG_MAC_TYPE_TH		0x32
472
+#define IWL_CFG_MAC_TYPE_QU		0x33
473
+#define IWL_CFG_MAC_TYPE_QUZ		0x35
474
+#define IWL_CFG_MAC_TYPE_QNJ		0x36
475
+#define IWL_CFG_MAC_TYPE_SNJ		0x42
476
+#define IWL_CFG_MAC_TYPE_MA		0x44
477
+
478
+#define IWL_CFG_RF_TYPE_TH		0x105
479
+#define IWL_CFG_RF_TYPE_TH1		0x108
480
+#define IWL_CFG_RF_TYPE_JF2		0x105
481
+#define IWL_CFG_RF_TYPE_JF1		0x108
482
+#define IWL_CFG_RF_TYPE_HR2		0x10A
483
+#define IWL_CFG_RF_TYPE_HR1		0x10C
484
+#define IWL_CFG_RF_TYPE_GF		0x10D
485
+#define IWL_CFG_RF_TYPE_MR		0x110
486
+
487
+#define IWL_CFG_RF_ID_TH		0x1
488
+#define IWL_CFG_RF_ID_TH1		0x1
489
+#define IWL_CFG_RF_ID_JF		0x3
490
+#define IWL_CFG_RF_ID_JF1		0x6
491
+#define IWL_CFG_RF_ID_JF1_DIV		0xA
492
+#define IWL_CFG_RF_ID_HR		0x7
493
+#define IWL_CFG_RF_ID_HR1		0x4
494
+
495
+#define IWL_CFG_NO_160			0x1
496
+#define IWL_CFG_160			0x0
497
+
498
+#define IWL_CFG_CORES_BT		0x0
499
+#define IWL_CFG_CORES_BT_GNSS		0x5
500
+
501
+#define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
502
+#define IWL_SUBDEVICE_NO_160(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
503
+#define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
504
+
505
+struct iwl_dev_info {
506
+	u16 device;
507
+	u16 subdevice;
508
+	u16 mac_type;
509
+	u16 rf_type;
510
+	u8 mac_step;
511
+	u8 rf_id;
512
+	u8 no_160;
513
+	u8 cores;
514
+	const struct iwl_cfg *cfg;
515
+	const char *name;
485516 };
486517 
487518 /*
488519  * This list declares the config structures for all devices.
489520  */
521
+extern const struct iwl_cfg_trans_params iwl9000_trans_cfg;
522
+extern const struct iwl_cfg_trans_params iwl9560_trans_cfg;
523
+extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg;
524
+extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg;
525
+extern const struct iwl_cfg_trans_params iwl_qnj_trans_cfg;
526
+extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg;
527
+extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg;
528
+extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg;
529
+extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg;
530
+extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg;
531
+extern const char iwl9162_name[];
532
+extern const char iwl9260_name[];
533
+extern const char iwl9260_1_name[];
534
+extern const char iwl9270_name[];
535
+extern const char iwl9461_name[];
536
+extern const char iwl9462_name[];
537
+extern const char iwl9560_name[];
538
+extern const char iwl9162_160_name[];
539
+extern const char iwl9260_160_name[];
540
+extern const char iwl9270_160_name[];
541
+extern const char iwl9461_160_name[];
542
+extern const char iwl9462_160_name[];
543
+extern const char iwl9560_160_name[];
544
+extern const char iwl9260_killer_1550_name[];
545
+extern const char iwl9560_killer_1550i_name[];
546
+extern const char iwl9560_killer_1550s_name[];
547
+extern const char iwl_ax200_name[];
548
+extern const char iwl_ax203_name[];
549
+extern const char iwl_ax201_name[];
550
+extern const char iwl_ax101_name[];
551
+extern const char iwl_ax200_killer_1650w_name[];
552
+extern const char iwl_ax200_killer_1650x_name[];
553
+extern const char iwl_ax201_killer_1650s_name[];
554
+extern const char iwl_ax201_killer_1650i_name[];
555
+extern const char iwl_ma_name[];
556
+extern const char iwl_ax211_name[];
557
+extern const char iwl_ax411_name[];
490558 #if IS_ENABLED(CONFIG_IWLDVM)
491559 extern const struct iwl_cfg iwl5300_agn_cfg;
492560 extern const struct iwl_cfg iwl5100_agn_cfg;
....@@ -552,40 +620,44 @@
552620 extern const struct iwl_cfg iwl8265_2ac_cfg;
553621 extern const struct iwl_cfg iwl8275_2ac_cfg;
554622 extern const struct iwl_cfg iwl4165_2ac_cfg;
555
-extern const struct iwl_cfg iwl9160_2ac_cfg;
556623 extern const struct iwl_cfg iwl9260_2ac_cfg;
557
-extern const struct iwl_cfg iwl9260_killer_2ac_cfg;
558
-extern const struct iwl_cfg iwl9270_2ac_cfg;
559
-extern const struct iwl_cfg iwl9460_2ac_cfg;
560
-extern const struct iwl_cfg iwl9560_2ac_cfg;
561
-extern const struct iwl_cfg iwl9460_2ac_cfg_soc;
562
-extern const struct iwl_cfg iwl9461_2ac_cfg_soc;
563
-extern const struct iwl_cfg iwl9462_2ac_cfg_soc;
624
+extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg;
625
+extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg;
626
+extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg;
627
+extern const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg;
564628 extern const struct iwl_cfg iwl9560_2ac_cfg_soc;
565
-extern const struct iwl_cfg iwl9560_killer_2ac_cfg_soc;
566
-extern const struct iwl_cfg iwl9560_killer_s_2ac_cfg_soc;
567
-extern const struct iwl_cfg iwl9460_2ac_cfg_shared_clk;
568
-extern const struct iwl_cfg iwl9461_2ac_cfg_shared_clk;
569
-extern const struct iwl_cfg iwl9462_2ac_cfg_shared_clk;
570
-extern const struct iwl_cfg iwl9560_2ac_cfg_shared_clk;
571
-extern const struct iwl_cfg iwl9560_killer_2ac_cfg_shared_clk;
572
-extern const struct iwl_cfg iwl9560_killer_s_2ac_cfg_shared_clk;
573
-extern const struct iwl_cfg iwl22000_2ac_cfg_hr;
574
-extern const struct iwl_cfg iwl22000_2ac_cfg_hr_cdb;
575
-extern const struct iwl_cfg iwl22000_2ac_cfg_jf;
576
-extern const struct iwl_cfg iwl22000_2ax_cfg_hr;
577
-extern const struct iwl_cfg iwl9461_2ac_cfg_qu_b0_jf_b0;
578
-extern const struct iwl_cfg iwl9462_2ac_cfg_qu_b0_jf_b0;
579
-extern const struct iwl_cfg iwl9560_2ac_cfg_qu_b0_jf_b0;
580
-extern const struct iwl_cfg killer1550i_2ac_cfg_qu_b0_jf_b0;
581
-extern const struct iwl_cfg killer1550s_2ac_cfg_qu_b0_jf_b0;
582
-extern const struct iwl_cfg iwl22000_2ax_cfg_jf;
583
-extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0_f0;
584
-extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0_f0;
585
-extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_b0;
586
-extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_jf_b0;
587
-extern const struct iwl_cfg iwl22000_2ax_cfg_qnj_hr_a0;
588
-extern const struct iwl_cfg iwl22560_2ax_cfg_su_cdb;
589
-#endif /* CPTCFG_IWLMVM || CPTCFG_IWLFMAC */
629
+extern const struct iwl_cfg iwl_qu_b0_hr1_b0;
630
+extern const struct iwl_cfg iwl_qu_c0_hr1_b0;
631
+extern const struct iwl_cfg iwl_quz_a0_hr1_b0;
632
+extern const struct iwl_cfg iwl_qu_b0_hr_b0;
633
+extern const struct iwl_cfg iwl_qu_c0_hr_b0;
634
+extern const struct iwl_cfg iwl_ax200_cfg_cc;
635
+extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
636
+extern const struct iwl_cfg iwl_ax201_cfg_qu_hr;
637
+extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0;
638
+extern const struct iwl_cfg iwl_ax201_cfg_quz_hr;
639
+extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
640
+extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
641
+extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
642
+extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
643
+extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
644
+extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
645
+extern const struct iwl_cfg killer1650x_2ax_cfg;
646
+extern const struct iwl_cfg killer1650w_2ax_cfg;
647
+extern const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg;
648
+extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_a0;
649
+extern const struct iwl_cfg iwlax210_2ax_cfg_so_hr_a0;
650
+extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0;
651
+extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long;
652
+extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0;
653
+extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0;
654
+extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long;
655
+extern const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0;
656
+extern const struct iwl_cfg iwlax211_cfg_snj_gf_a0;
657
+extern const struct iwl_cfg iwlax201_cfg_snj_hr_b0;
658
+extern const struct iwl_cfg iwl_cfg_ma_a0_gf_a0;
659
+extern const struct iwl_cfg iwl_cfg_ma_a0_mr_a0;
660
+extern const struct iwl_cfg iwl_cfg_snj_a0_mr_a0;
661
+#endif /* CONFIG_IWLMVM */
590662 
591663 #endif /* __IWL_CONFIG_H__ */